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EP3C5E144C7N Datasheet, PDF (25/34 Pages) Altera Corporation – 1. Cyclone III Device Datasheet | |||
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Chapter 1: Cyclone III Device Datasheet
Switching Characteristics
1â25
Table 1â34. Cyclone III Devices Memory Output Clock Jitter Specifications (1), (2) (Part 2 of 2)
Parameter
Symbol
Min
Max
Unit
Duty cycle jitter
tJIT(duty)
-150
150
ps
Notes to Table 1â34:
(1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2 standard.
(2) The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL output routed on a global
clock network.
Duty Cycle Distortion Specifications
Table 1â35 lists the worst case duty cycle distortion for Cyclone III devices.
Table 1â35. Duty Cycle Distortion on Cyclone III Devices I/O Pins (1), (2)
Symbol
Output Duty Cycle
C6
C7, I7
C8, A7
Unit
Min Max Min Max Min Max
45
55
45
55
45
55
%
Notes to Table 1â35:
(1) Duty cycle distortion specification applies to clock outputs from PLLs, global clock tree, and IOE driving dedicated
and general purpose I/O pins.
(2) Cyclone III devices meet specified duty cycle distortion at maximum output toggle rate for each combination of
I/O standard and current strength.
OCT Calibration Timing Specification
Table 1â36 lists the duration of calibration for series OCT with calibration at device
power-up for Cyclone III devices.
Table 1â36. Cyclone III Devices Timing Specification for Series OCT with Calibration at Device
Power-Up (1)
Symbol
Description
Maximum
Unit
tOCTCAL
Duration of series OCT with
calibration at device power-up
20
µs
Notes to Table 1â36:
(1) OCT calibration takes place after device configuration, before entering user mode.
IOE Programmable Delay
Table 1â37 and Table 1â38 list IOE programmable delay for Cyclone III devices.
Table 1â37. Cyclone III Devices IOE Programmable Delay on Column Pins (1), (2) (Part 1 of 2)
Parameter
Paths
Affected
Number
of
Settings
Min
Offset
Fast Corner
A7, I7 C6
Max Offset
Slow Corner
C6
C7
C8
I7
Unit
A7
Input delay from pin to
internal cells
Pad to I/O
dataout to
core
7
0 1.211 1.314 2.175 2.32 2.386 2.366 2.49 ns
Input delay from pin to Pad to I/O
input register
input register
8
0 1.203 1.307 2.19 2.387 2.54 2.43 2.545 ns
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
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