EPC16UC88N Datasheet, PDF (28/36 Pages) Altera Corporation – Enhanced Configuration (EPC) Devices Datasheet

Page 28
IEEE Std. 1149.1 (JTAG) Boundary-Scan
You can also program the EPC devices using the Quartus II software, the Altera
Programming Unit (APU), and the appropriate configuration device programming
adapter. Table 12 lists which programming adapter to use with each EPC device.
Table 12. Programming Adapters
Device
EPC16
EPC8
EPC4
Package
88-pin UFBGA
100-pin PQFP
100-pin PQFP
100-pin PQFP
Adapter
PLMUEPC-88
PLMQEPC-100
PLMQEPC-100
PLMQEPC-100
IEEE Std. 1149.1 (JTAG) Boundary-Scan
The EPC device provides JTAG BST circuitry that complies with the IEEE Std.
1149.1-1990 specification. JTAG BST can be performed before or after configuration,
but not during configuration.
Figure 6 shows the timing requirements for the JTAG signals.
Figure 6. JTAG Timing Waveforms
TMS
TDI
TCK
TDO
Signal
to be
Captured
Signal
to be
Driven
t_JCH
t_JCP
t_JCL
t_JPSU
t _JPZX
t_JSSU
t_JSZX
t_JPCO
t_JSH
t_JSCO
t_JPH
t_JPXZ
t_JSXZ
Table 13 lists the timing parameters and values for the EPC device.
Table 13. JTAG Timing Parameters and Values (Part 1 of 2)
Symbol
t_JCP
t_JCH
t_JCL
t_JPSU
t_JPH
t_JPCO
t_JPZX
Parameter
TCK clock period
TCK clock high time
TCK clock low time
JTAG port setup time
JTAG port hold time
JTAG port clock output
JTAG port high impedance to valid output
Min
Max
Unit
100
—
ns
50
—
ns
50
—
ns
20
—
ns
45
—
ns
—
25
ns
—
25
ns
Enhanced Configuration (EPC) Devices Datasheet
January 2012 Altera Corporation