EP4CGX75CF23I7N Datasheet, PDF (25/42 Pages) Altera Corporation – Cyclone IV Device Datasheet

Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
1–25
Table 1–25. PLL Specifications for Cyclone IV Devices ^{(1), (2)} (Part 2 of 2)
Symbol
Parameter
Min Typ Max Unit
t_DLOCK
Time required to lock dynamically (after switchover,
reconfiguring any non-post-scale counters/delays or
——
1
ms
areset is deasserted)
t_{OUTJITTER_PERIOD_DEDCLK} ⁽⁶⁾
t_{OUTJITTER_CCJ_DEDCLK} ⁽⁶⁾
t_{OUTJITTER_PERIOD_IO} ⁽⁶⁾
t_{OUTJITTER_CCJ_IO} ⁽⁶⁾
t_{PLL_PSERR}
t_ARESET
Dedicated clock output period jitter
F_OUT  100 MHz
F_OUT < 100 MHz
Dedicated clock output cycle-to-cycle jitter
F_OUT  100 MHz
F_OUT < 100 MHz
Regular I/O period jitter
F_OUT  100 MHz
F_OUT < 100 MHz
Regular I/O cycle-to-cycle jitter
F_OUT  100 MHz
F_OUT < 100 MHz
Accuracy of PLL phase shift
Minimum pulse width on areset signal.
— — 300
ps
—
— 30
mUI
— — 300
ps
—
— 30
mUI
— — 650
ps
—
— 75
mUI
— — 650
ps
—
— 75
mUI
— — ±50
ps
10 — —
ns
t_CONFIGPLL
Time required to reconfigure scan chains for PLLs
—
3.5 ⁽⁷⁾
—
SCANCLK
cycles
f_SCANCLK
scanclk frequency
— — 100 MHz
t_{CASC_OUTJITTER_PERIOD_DEDCLK}
(8), (9)
Period jitter for dedicated clock output in cascaded
PLLs (F_OUT  100 MHz)
Period jitter for dedicated clock output in cascaded
PLLs (F_OUT  100 MHz)
— — 425
ps
— — 42.5 mUI
Notes to Table 1–25:
(1) This table is applicable for general purpose PLLs and multipurpose PLLs.
(2) You must connect V_{CCD_PLL} to V_CCINT through the decoupling capacitor and ferrite bead.
(3) This parameter is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
standard.
(4) The V_CO frequency reported by the Quartus II software in the PLL Summary section of the compilation report takes into consideration the V_CO
post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the f_VCO specification.
(5) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source that is less
than 200 ps.
(6) Peak-to-peak jitter with a probability level of 10^–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies
to the intrinsic jitter of the PLL when an input jitter of 30 ps is applied.
(7) With 100-MHz scanclk frequency.
(8) The cascaded PLLs specification is applicable only with the following conditions:
■ Upstream PLL—0.59 MHz  Upstream PLL bandwidth < 1 MHz
■ Downstream PLL—Downstream PLL bandwidth > 2 MHz
(9) PLL cascading is not supported for transceiver applications.
December 2013 Altera Corporation
Cyclone IV Device Handbook,
Volume 3