EP4CGX75CF23I7N Datasheet, PDF (17/42 Pages) Altera Corporation – Cyclone IV Device Datasheet

Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
1–17
Transceiver Performance Specifications
Table 1–21 lists the Cyclone IV GX transceiver specifications.
Table 1–21. Transceiver Specification for Cyclone IV GX Devices (Part 1 of 4)
Symbol/
Description
Conditions
C6
C7, I7
C8
Unit
Min Typ
Max Min Typ Max Min Typ Max
Reference Clock
Supported I/O
Standards
Input frequency
from REFCLK input
pins
Spread-spectrum
modulating clock
frequency
Spread-spectrum
downspread
Peak-to-peak
differential input
voltage
V_ICM (AC coupled)
V_ICM (DC coupled)
Transmitter REFCLK
Phase Noise ⁽¹⁾
Transmitter REFCLK
Total Jitter ⁽¹⁾
R_ref
—
Physical interface
for PCI Express
(PIPE) mode
PIPE mode
—
—
HCSL I/O
standard for PCIe
reference clock
Frequency offset
= 1 MHz – 8 MHZ
—
1.2 V PCML, 1.5 V PCML, 3.3 V PCML, Differential LVPECL, LVDS, HCSL
50 — 156.25 50 — 156.25 50 — 156.25
30 —
33
—
0 to
–0.5%
—
0.1 —
1.6
1100 ± 5%
250 —
550
30
—
33
30
—
33
—
0 to
–0.5%
—
—
0 to
–0.5%
—
0.1
—
1.6 0.1
—
1.6
1100 ± 5%
1100 ± 5%
250 — 550 250 —
550
—
—
–123
——
42.3
—
2000
± 1%
—
— — –123 — — –123
—
— 42.3 —
—
42.3
—
2000
± 1%
—
—
2000
± 1%
—
MHz
kHz
—
V
mV
mV
dBc/Hz
ps

Transceiver Clock
cal_blk_clk clock
frequency
—
10 —
fixedclk clock
frequency
PCIe Receiver
Detect
— 125
reconfig_clk
clock frequency
Dynamic
2.5/
reconfiguration 37.5 —
clock frequency
(2)
Delta time between
—
——
reconfig_clk
Transceiver block
minimum
power-down pulse
width
—
—
1
125
10 — 125 10 —
125 MHz
—
— 125 —
— 125
—
MHz
2.5/
2.5/
50
37.5 —
50 37.5 —
(2)
(2)
50 MHz
2
——
2
——
2
ms
—
—
1
——
1
—
µs
December 2013 Altera Corporation
Cyclone IV Device Handbook,
Volume 3