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EP4CE15F23C6N Datasheet, PDF (25/42 Pages) Altera Corporation – This section lists the I/O leakage current, pin capacitance, on-chip termination (OCT) tolerance, and bus hold specifications for Cyclone IV devices. | |||
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Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
1â25
Table 1â25. PLL Specifications for Cyclone IV Devices (1), (2) (Part 2 of 2)
Symbol
Parameter
Min Typ Max Unit
tDLOCK
Time required to lock dynamically (after switchover,
reconfiguring any non-post-scale counters/delays or
ââ
1
ms
areset is deasserted)
tOUTJITTER_PERIOD_DEDCLK (6)
tOUTJITTER_CCJ_DEDCLK (6)
tOUTJITTER_PERIOD_IO (6)
tOUTJITTER_CCJ_IO (6)
tPLL_PSERR
tARESET
Dedicated clock output period jitter
FOUT ï³ 100 MHz
FOUT < 100 MHz
Dedicated clock output cycle-to-cycle jitter
FOUT ï³ 100 MHz
FOUT < 100 MHz
Regular I/O period jitter
FOUT ï³ 100 MHz
FOUT < 100 MHz
Regular I/O cycle-to-cycle jitter
FOUT ï³ 100 MHz
FOUT < 100 MHz
Accuracy of PLL phase shift
Minimum pulse width on areset signal.
â â 300
ps
â
â 30
mUI
â â 300
ps
â
â 30
mUI
â â 650
ps
â
â 75
mUI
â â 650
ps
â
â 75
mUI
â â ±50
ps
10 â â
ns
tCONFIGPLL
Time required to reconfigure scan chains for PLLs
â
3.5 (7)
â
SCANCLK
cycles
fSCANCLK
scanclk frequency
â â 100 MHz
tCASC_OUTJITTER_PERIOD_DEDCLK
(8), (9)
Period jitter for dedicated clock output in cascaded
PLLs (FOUT ï³ 100 MHz)
Period jitter for dedicated clock output in cascaded
PLLs (FOUT ï¼ 100 MHz)
â â 425
ps
â â 42.5 mUI
Notes to Table 1â25:
(1) This table is applicable for general purpose PLLs and multipurpose PLLs.
(2) You must connect VCCD_PLL to VCCINT through the decoupling capacitor and ferrite bead.
(3) This parameter is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
standard.
(4) The VCO frequency reported by the Quartus II software in the PLL Summary section of the compilation report takes into consideration the VCO
post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification.
(5) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source that is less
than 200 ps.
(6) Peak-to-peak jitter with a probability level of 10â12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies
to the intrinsic jitter of the PLL when an input jitter of 30 ps is applied.
(7) With 100-MHz scanclk frequency.
(8) The cascaded PLLs specification is applicable only with the following conditions:
â Upstream PLLâ0.59 MHz ï£ Upstream PLL bandwidth < 1 MHz
â Downstream PLLâDownstream PLL bandwidth > 2 MHz
(9) PLL cascading is not supported for transceiver applications.
December 2013 Altera Corporation
Cyclone IV Device Handbook,
Volume 3
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