EP1S40F1020C5 Datasheet, PDF (219/292 Pages) Altera Corporation – Stratix Device Handbook, Volume 1

DC & Switching Characteristics
Tables 4–61 through 4–66 show the external timing parameters on column
and row pins for EP1S20 devices.
Table 4–61. EP1S20 External I/O Timing on Column Pins Using Fast Regional Clock Networks Note (1)
Parameter
-5 Speed Grade
Min
Max
-6 Speed Grade
Min
Max
-7 Speed Grade
Min
Max
-8 Speed Grade
Unit
Min
Max
t_INSU
t_INH
t_OUTCO
t_XZ
t_ZX
2.065
2.245
2.576
NA
ns
0.000
0.000
0.000
NA
ns
2.283 4.622 2.283 4.916 2.283 5.310
NA
NA
ns
2.223 4.496 2.223 4.784 2.223 5.186
NA
NA
ns
2.223 4.496 2.223 4.784 2.223 5.186
NA
NA
ns
Table 4–62. EP1S20 External I/O Timing on Column Pins Using Regional Clock Networks Note (1)
-5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade
Parameter
Unit
Min
Max
Min
Max
Min
Max
Min
Max
t_INSU
t_INH
t_OUTCO
t_XZ
t_ZX
t_INSUPLL
t_INHPLL
t_OUTCOPLL
t_XZPLL
t_ZXPLL
1.541
1.680
1.931
NA
0.000
0.000
0.000
NA
2.597 5.146 2.597 5.481 2.597 5.955
NA
2.537 5.020 2.537 5.349 2.537 5.831
NA
2.537 5.020 2.537 5.349 2.537 5.831
NA
0.777
0.818
0.937
NA
0.000
0.000
0.000
NA
1.296 2.690 1.296 2.801 1.296 2.876
NA
1.236 2.564 1.236 2.669 1.236 2.752
NA
1.236 2.564 1.236 2.669 1.236 2.752
NA
ns
ns
NA
ns
NA
ns
NA
ns
ns
ns
NA
ns
NA
ns
NA
ns
Altera Corporation
January 2006
4–39
Stratix Device Handbook, Volume 1