EP1S40F1020C5 Datasheet, PDF (121/292 Pages) Altera Corporation – Stratix Device Handbook, Volume 1

Stratix Architecture
VCO period from up to eight taps for individual fine step selection. Also,
each clock output counter can use a unique initial count setting to achieve
individual coarse shift selection in steps of one VCO period. The
combination of coarse and fine shifts allows phase shifting for the entire
input clock period.
The equation to determine the precision of the phase shifting in degrees
is: 45° ÷ post-scale counter value. Therefore, the maximum step size is
45° , and smaller steps are possible depending on the multiplication and
division ratio necessary on the output counter port.
This type of phase shift provides the highest precision since it is the least
sensitive to process, supply, and temperature variation.
Clock Delay
In addition to the phase shift feature, the ability to fine tune the Δt clock
delay provides advanced time delay shift control on each of the four PLL
outputs. There are time delays for each post-scale counter (e, g, or l) from
the PLL, the n counter, and m counter. Each of these can shift in 250-ps
increments for a range of 3.0 ns. The m delay shifts all outputs earlier in
time, while n delay shifts all outputs later in time. Individual delays on
post-scale counters (e, g, and l) provide positive delay for each output.
Table 2–21 shows the combined delay for each output for normal or zero
delay buffer mode where Δt_e, Δt_g, or Δt_l is unique for each PLL output.
The t_OUTPUT for a single output can range from –3 ns to +6 ns. The total
delay shift difference between any two PLL outputs, however, must be
less than ±3 ns. For example, shifts on two outputs of –1 and +2 ns is
allowed, but not –1 and +2.5 ns because these shifts would result in a
difference of 3.5 ns. If the design uses external feedback, the Δt_e delay will
remove delay from outputs, represented by a negative sign (see
Table 2–21). This effect occurs because the Δt_e delay is then part of the
feedback loop.
Table 2–21. Output Clock Delay for Enhanced PLLs
Normal or Zero Delay Buffer Mode
External Feedback Mode
Δt_eOUTPUT = Δt_n −Δt_m + Δt_e
Δt_gOUTPUT = Δt_n −Δt_m + Δt_g
Δt_lOUTPUT = Δt_n −Δt_m + Δt_l
Δt_eOUTPUT = Δt_n −Δt_m −Δt_e (1)
Δt_gOUTPUT = Δt_n −Δt_m + Δt_g
Δt_lOUTPUT = Δt_n −Δt_m + Δt_l
Note to Table 2–21:
(1) Δt_e removes delay from outputs in external feedback mode.
Altera Corporation
July 2005
2–97
Stratix Device Handbook, Volume 1