EP1S40F1020C5 Datasheet, PDF (128/292 Pages) Altera Corporation – Stratix Device Handbook, Volume 1

I/O Structure
I/O Structure
Control Signals
The fast PLL has the same lock output, pllenable input, and areset
input control signals as the enhanced PLL.
If the input clock stops and causes the PLL to lose lock, then the PLL must
be reset for correct phase shift operation.
For more information on high-speed differential I/O support, see “High-
Speed Differential I/O Support” on page 2–130.
IOEs provide many features, including:
■ Dedicated differential and single-ended I/O buffers
■ 3.3-V, 64-bit, 66-MHz PCI compliance
■ 3.3-V, 64-bit, 133-MHz PCI-X 1.0 compliance
■ Joint Test Action Group (JTAG) boundary-scan test (BST) support
■ Differential on-chip termination for LVDS I/O standard
■ Programmable pull-up during configuration
■ Output drive strength control
■ Slew-rate control
■ Tri-state buffers
■ Bus-hold circuitry
■ Programmable pull-up resistors
■ Programmable input and output delays
■ Open-drain outputs
■ DQ and DQS I/O pins
■ Double-data rate (DDR) Registers
The IOE in Stratix devices contains a bidirectional I/O buffer, six
registers, and a latch for a complete embedded bidirectional single data
rate or DDR transfer. Figure 2–59 shows the Stratix IOE structure. The
IOE contains two input registers (plus a latch), two output registers, and
two output enable registers. The design can use both input registers and
the latch to capture DDR input and both output registers to drive DDR
outputs. Additionally, the design can use the output enable (OE) register
for fast clock-to-output enable timing. The negative edge-clocked OE
register is used for DDR SDRAM interfacing. The Quartus II software
automatically duplicates a single OE register that controls multiple
output or bidirectional pins.
2–104
Stratix Device Handbook, Volume 1
Altera Corporation
July 2005