EP53A7HQI Datasheet, PDF (15/19 Pages) Altera Corporation – 1A PowerSoC Light Load Mode Buck Regulator with Integrated Inductor

EP53A7LQI/EP53A7HQI
100 Ohm
V_IN
4.7uF
PVIN
V_Sense
V_OUT
AVIN
Ra
ENABLE
V_FB
VS0
VS1
Rb
LLM
VS2 _{PGND AGND}
V_OUT
10µF
Figure 11: EP53A7LQI using external divider
The output voltage is selected by the following
formula:
( ) V_OUT
= 0.6V
1+
Ra
Rb
R_a must be chosen as 237KΩ to maintain loop
gain. Then R_b is given as:
142.2 x10 ³
R⁼
Ω
b _{VOUT − 0.6}
V_OUT can be programmed over the range of
0.6V to (V_IN – 0.5V).
NOTE: Dynamic Voltage Scaling is not allowed
between internal preset voltages and external
divider.
NOTE: LLM is not functional when using the
external divider option. Tie the LLM pin to
AGND when using this option.
EP53A7HQI High VID Range
Programming
The EP53A7HQI V_OUT settings are optimized
for higher nominal voltages such as those
required to power IO, RF, or IC memory. The
preset voltages range from 1.8V to 3.3V.
There are eight (8) preset output voltage
settings. The EP53A7HQI does not have an
external divider option. As with the
EP53A7LQI, the VID pin settings can be
changed while the device is enabled.
or alternatively can be driven by standard logic
levels. Logic levels are defined in the electrical
characteristics table. Any level between the
logic high and logic low is indeterminate.
These pins must not be left floating.
Table 3: EP53A7HQI VID Voltage Select Settings
VS2
VS1
VS0
VOUT
0
0
0
3.3
0
0
1
3.0
0
1
0
2.9
0
1
1
2.6
1
0
0
2.5
1
0
1
2.2
1
1
0
2.1
1
1
1
1.8
Power-Up/Down Sequencing
During power-up, ENABLE should not be
asserted before PVIN, and PVIN should not be
asserted before AVIN. The PVIN should never
be powered when AVIN is off. During power
down, the AVIN should not be powered down
before the PVIN. Tying PVIN and AVIN or all
three pins (AVIN, PVIN, ENABLE) together
during power up or power down meets these
requirements.
Pre-Bias Start-up
The EP53A7xQI does not support startup into
a pre-biased condition. Be sure the output
capacitors are not charged or the output of the
EP53A7xQI is not pre-biased when the
EP53A7xQI is first enabled.
Input Filter Capacitor
The input filter capacitor requirement is a
4.7µF 0402 or 0603 low ESR MLCC capacitor.
Output Filter Capacitor
The output filter capacitor requirement is a
minimum of 10µF 0805 MLCC. Ripple
performance can be improved by using 2x10µF
0603 or 2x10µF 0805 MLCC capacitors.
Table 3 shows the VS0-VS2 pin logic states for
the EP53A7HQI and the associated output
voltage levels. A logic “1” indicates a
connection to AVIN or to a “high” logic voltage
level. A logic “0” indicates a connection to
AGND or to a “low” logic voltage level. These
pins can be either hardwired to AVIN or AGND
The maximum output filter capacitance next to
the output pins of the device is 60µF low ESR
MLCC capacitance. V_OUT has to be sensed at
the last output filter capacitor next to the
EP53A7xQI.
Additional bulk capacitance for decoupling and
01543
15
October 11, 2013
www.altera.com/enpirion
Rev D