EP53A7HQI Datasheet, PDF (14/19 Pages) Altera Corporation – 1A PowerSoC Light Load Mode Buck Regulator with Integrated Inductor

EP53A7LQI/EP53A7HQI
Application Information
100 ohm
V_IN
4.7µF
PVIN
V_OUT
AVIN
V_SENSE
ENABLE
LLM
VS0
VS1
VS2
PGND AGND
V_OUT
10µF
which in turn is connected to the non-inverting
input of the error amplifier. This allows the use
of a single feedback divider with constant loop
gain and optimum compensation, independent
of the output voltage selected.
NOTE: The VID pins must not be left floating.
EP53A7L Low VID Range Programming
Figure 9: Application Circuit, EP53A7HQI. Note that
all control signals should be connected to an
external control signal, AVIN or AGND.
100 ohm
V_IN
4.7µF
PVIN
V_OUT
AVIN
V_SENSE
ENABLE
LLM
VS0
V_FB
VS1
VS2
PGND AGND
V_OUT
10µF
Figure 10: Application Circuit, EP53A7LQI showing
the V_FB function.
Output Voltage Programming
The EP53A7xQI utilizes a 3-pin VID to program
the output voltage value. The VID is available
in two sets of output VID programming ranges.
The VID pins should be connected either to an
external control signal, AVIN or to AGND to
avoid noise coupling into the device. The VID
pins must not be left floating.
The “Low” range is optimized for low voltage
applications. It comes with preset VID settings
ranging from 0.80V and 1.5V. This VID set
also has an external divider option.
To specify this VID range, order part number
EP53A7LQI.
The “High” VID set provides output voltage
settings ranging from 1.8V to 3.3V. This
version does not have an external divider
option. To specify this VID range, order part
number EP53A7HQI.
Internally, the output of the VID multiplexer
sets the value for the voltage reference DAC,
The EP53A7LQI is designed to provide a high
degree of flexibility in powering applications
that require low V_OUT settings and dynamic
voltage scaling (DVS). The device employs a
3-pin VID architecture that allows the user to
choose one of seven (7) preset output voltage
settings, or the user can select an external
voltage divider option. The VID pin settings
can be changed on the fly to implement glitch-
free voltage scaling.
Table 2: EP53A7LQI VID Voltage Select Settings
VS2
VS1
VS0
VOUT
0
0
0
1.50
0
0
1
1.45
0
1
0
1.20
0
1
1
1.15
1
0
0
1.10
1
0
1
1.05
1
1
0
0.8
1
1
1
EXT
Table 2 shows the VS2-VS0 pin logic states for
the EP53A7LQI and the associated output
voltage levels. A logic “1” indicates a
connection to AVIN or to a “high” logic voltage
level. A logic “0” indicates a connection to
AGND or to a “low” logic voltage level. These
pins can be either hardwired to AVIN or AGND
or alternatively can be driven by standard logic
levels. Logic levels are defined in the electrical
characteristics table. Any level between the
logic high and logic low is indeterminate.
EP53A7LQI External Voltage Divider
The external divider option is chosen by
connecting VID pins VS2-VS0 to AVIN or a
logic “1” or “high”. The EP53A7LQI uses a
separate feedback pin, V_FB, when using the
external divider. V_SENSE must be connected to
V_OUT as indicated in Figure 11.
01543
14
October 11, 2013
www.altera.com/enpirion
Rev D