EP5357XUI Datasheet, PDF (14/19 Pages) Altera Corporation – 600mA PowerSoC Synchronous Buck Regulator With Integrated Inductor

EP5357LUI External Voltage Divider
The external divider option is chosen by
connecting VID pins VS2-VS0 to V_IN or a logic
“1” or “high”. The EP5357LUI uses a separate
feedback pin, V_FB, when using the external
divider. V_SENSE must be connected to V_OUT as
indicated in Figure 11. The output voltage is
selected by the following formula:
( ) V_OUT
= 0.6V
1+
Ra
Rb
R_a must be chosen as 237KΩ to maintain loop
gain. Then R_b is given as:
R ^{= 142.2x103 Ω}
b _{VOUT − 0.6}
V_OUT can be programmed over the range of
0.6V to (V_IN – 0.25V).
NOTE: Dynamic Voltage Scaling is not allowed
between internal preset voltages and external
divider.
NOTE: LLM is not functional when using the
external divider option. Tie the LLM pin to
AGND.
V_IN
PVIN
AVIN
V_Sense
V_OUT
V_OUT
4.7uF
ENABLE
Ra
10µF
V_FB
VS0
VS1
Rb
VS2 _{PGND AGND}
EP5357LUI/EP5357HUI
connection to AVIN or to a “high” logic voltage
level. A logic “0” indicates a connection to
AGND or to a “low” logic voltage level. These
pins can be either hardwired to AVIN or AGND
or alternatively can be driven by standard logic
levels. Logic levels are defined in the electrical
characteristics table. Any level between the
logic high and logic low is indeterminate.
These pins must not be left floating.
Table 3: EP5357HUI VID Voltage Select Settings
VS2
VS1
VS0
VOUT
0
0
0
3.3
0
0
1
3.0
0
1
0
2.9
0
1
1
2.6
1
0
0
2.5
1
0
1
2.2
1
1
0
2.1
1
1
1
1.8
Power-Up/Down Sequencing
During power-up, ENABLE should not be
asserted before PVIN, and PVIN should not be
asserted before AVIN. The PVIN should never
be powered when AVIN is off. During power
down, the AVIN should not be powered down
before the PVIN. Tying PVIN and AVIN or all
three pins (AVIN, PVIN, ENABLE) together
during power up or power down meets these
requirements.
Figure 11: EP5357LUI using external divider
EP5357HUI High VID Range Programming
The EP5357HUI V_OUT settings are optimized
for higher nominal voltages such as those
required to power IO, RF, or IC memory. The
preset voltages range from 1.8V to 3.3V.
There are eight (8) preset output voltage
settings. The EP5357HUI does not have an
external divider option. As with the
EP5357LUI, the VID pin settings can be
changed while the device is enabled.
Table 3 shows the VS0-VS2 pin logic states for
the EP5357HUI and the associated output
voltage levels. A logic “1” indicates a
Pre-Bias Start-up
The EP5357xUI does not support startup into a
pre-biased condition. Be sure the output
capacitors are not charged or the output of the
EP5357xUI is not pre-biased when the
EP5357xUI is first enabled.
Input Filter Capacitor
For I_LOAD ≤ 500mA, C_IN = 2.2uF
For I_LOAD > 500mA C_IN = 4.7uF.
0402 capacitor case size is acceptable.
The input capacitor must use a X5R or X7R or
equivalent dielectric formulation. Y5V or
equivalent dielectric formulations lose
capacitance with frequency, bias, and with
03409
14
October 11, 2013
www.altera.com/enpirion
Rev E