ASM5I9773A Datasheet, PDF (8/16 Pages) Alliance Semiconductor Corporation – 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer

June 2005
ASM5I9773A
rev 0. 3
AC Electrical Specifications (VDD = 2.5V ± 5%, T_A = – 40°C to + 85°C)⁹
Parameter
Description
Condition
Min
Typ
Max Unit
Skew within Bank A
-
-
75
t_sk(O)
Output-to-Output Skew
Skew within Bank B
-
-
100
pS
Skew within Bank C
-
-
150
t_sk(B)
Bank-to-Bank Skew
-
-
400
pS
t_{PLZ, HZ}
Output Disable Time
-
-
10
nS
t_{PZL, ZH}
Output Enable Time
-
-
10
nS
÷4 Feedback
-
1.3 - 2.0
-
÷6 Feedback
-
0.7 - 1.3
-
÷8 Feedback
-
0.9 - 1.3
-
BW
PLL Closed Loop Bandwidth (-3dB) ÷10 Feedback
-
0.6 - 1.1
-
MHz
÷12 Feedback
-
0.6 - 0.9
-
÷16 Feedback
-
0.4 - 0.6
-
÷20 Feedback
-
0.6 - 0.9
-
t_JIT(CC)
Cycle-to-Cycle Jitter
Same frequency
(125 MHz) RMS (1σ)
-
7
30
Same frequency
-
-
150
pS
Multiple frequencies
-
-
435
t_JIT(PER)
Period Jitter
Same frequency
(125 MHz) RMS (1σ)
-
6
30
Same frequency
-
45
75
pS
Multiple frequencies
-
-
235
t_JIT(φ)
I/O Phase Jitter
-
-
150
pS
t_LOCK
Maximum PLL Lock Time
-
-
1
mS
Notes:
9. AC characteristics apply for parallel output termination of 50Ω to V_TT. Outputs are at same supply voltage unless otherwise stated. Parameters are guaranteed
by characterization and are not 100% tested.
2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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