ASM5I9773A Datasheet, PDF (1/16 Pages) Alliance Semiconductor Corporation – 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer

June 2005
rev 0.3
ASM5I9773A
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
Features
ƒ Output frequency range: 8.33MHz to 200MHz
ƒ Input frequency range: 6.25MHz to 125MHz
ƒ 2.5V or 3.3V operation
ƒ Split 2.5V / 3.3V outputs
ƒ ±2%( max ) Output duty cycle variation
ƒ 12 Clock outputs: drive up to 24 clock lines
ƒ One feedback output
ƒ Three reference clock inputs: LVPECL or LVCMOS
ƒ 300pS ( max ) output-output skew
ƒ Phase-locked loop (PLL) bypass mode
ƒ ‘SpreadTrak’
ƒ Output enable/disable
ƒ Pin-compatible with CY29773, MPC9773 and
MPC973
ƒ Industrial temperature range: –40°C to +85°C
ƒ 52pin 1.0mm TQFP package
ƒ RoHS Compliance
Functional Description
The ASM5I9773A is a low-voltage high-performance
200-MHz PLL-based zero delay buffer designed for high
speed clock distribution applications.
The ASM5I9773A features one LVPECL and two LVCMOS
reference clock inputs and provides 12 outputs partitioned
in three banks of four outputs each. Each bank divides the
VCO output per SEL(A:C) settings (see Table 2. Function
Table (Configuration Controls)). These dividers allow
output-to-input ratios of 8:1, 6:1, 5:1, 4:1, 3:1, 8:3, 5:2, 2:1,
5:3, 3:2, 4:3, 5:4, 1:1, and 5:6. Each LVCMOS-compatible
output can drive 50Ω series- or parallel-terminated
transmission lines. For series-terminated transmission
lines, each output can drive one or two traces, giving the
device an effective fanout of 1:24.
The PLL is ensured stable, given that the VCO is
configured to run between 200 MHz to 500 MHz. This
allows a wide range of output frequencies, from 8 MHz to
200 MHz. For normal operation, the external feedback
input FB_IN is connected to the feedback output FB_OUT.
The internal VCO is running at multiples of the input
reference clock set by the feedback divider (see Table 1.
Frequency Table).
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully
static and the minimum input clock frequency specification
does not apply.
Alliance Semiconductor
2575, Augustine Drive • Santa Clara, CA • Tel: [phone] • Fax: [phone] • www.alsc.com
Notice: The information in this document is subject to change without notice.