ASM5I9773A Datasheet, PDF (10/16 Pages) Alliance Semiconductor Corporation – 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer

June 2005
ASM5I9773A
rev 0. 3
AC Electrical Specifications (VDD = 3.3V ±5%, T_A = –40°C to +85°C)¹¹
Parameter
Description
f_MAX
Maximum Output Frequency
f_SCLK
DC
t_r, t_f
t(φ)
t_sk(O)
t_sk(B)
t_{PLZ, HZ}
t_{PZL, ZH}
Serial Clock Frequency
Output Duty Cycle
Output Rise/Fall times
Propagation Delay
(static phase offset)
Output-to-Output Skew
Bank-to-Bank Skew
Output Disable Time
Output Enable Time
BW
PLL Closed Loop Bandwidth (–3 dB)
t_JIT(CC)
Cycle-to-Cycle Jitter
t_JIT(PER)
t_JIT(φ)
t_LOCK
Period Jitter
I/O Phase Jitter
Maximum PLL Lock Time
Condition
÷2 Output
÷4 Output
÷6 Output
÷8 Output
÷10 Output
÷12 Output
÷16 Output
÷20 Output
÷24 Output
f_MAX < 100 MHz
f_MAX > 100 MHz
0.55V to 2.4V
TCLK to FB_IN,
same VDD
PCLK to FB_IN,
same VDD
Skew within Bank A
Skew within Bank B
Skew within Bank C
÷4 Feedback
÷6 Feedback
÷8 Feedback
÷10 Feedback
÷12 Feedback
÷16 Feedback
÷20 Feedback
Same frequency
(125 MHz) RMS (1σ)
Same frequency
Multiple frequencies
Same frequency
(125 MHz) RMS (1σ)
Same frequency
Multiple frequencies
I/O same VDD
Min
Typ
Max Unit
100
-
200
50
-
125
MHz
33.3
-
83.3
25
-
62.5
20
-
50
16.6
-
41.6
12.5
-
31.25 MHz
10
-
25
8.3
-
20.8
-
-
20
MHz
48
-
52
%
45
-
55
0.1
-
1.0
nS
-125
-
125
pS
-125
-
125
-
-
75
-
-
100
pS
-
-
150
-
-
325
pS
-
-
8
nS
-
-
8
nS
-
1.3–2.0
-
-
0.7–1.3
-
-
0.9–1.3
-
-
0.6–1.1
-
MHz
-
0.6–0.9
-
-
0.4–0.6
-
-
0.6–0.9
-
-
7
30
-
-
100
pS
-
-
375
-
6
30
-
45
75
pS
-
-
225
-
-
150
pS
-
-
1
mS
Notes:
11. AC characteristics apply for parallel output termination of 50Ω to V_TT. Outputs are at same supply voltage unless otherwise stated. Parameters are
guaranteed by characterization and are not 100% tested.
2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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