AS4C64M16MD2-25BCN Datasheet, PDF (19/129 Pages) Alliance Semiconductor Corporation – Configurable Drive Strength

AS4C64M16MD2-25BCN
AS4C32M32MD2-25BCN
Table 7 – LPDDR2- SX Non Wrap Restrictions
1Gb
Not across full page boundary
x16
3FE, 3FF, 000, 001
x32
1FE, 1FF, 000, 001
Not across sub page boundary
x16
1FE, 1FF, 200, 201
x32
None
NOTE 1 Non - wrap BL =4 data-orders shown above are prohibited
MR2 Device Feature 2 (MA <7:0> =02H) :
OP7
OP6
OP5
(RFU)
OP4
OP3
OP2
OP1
RL & WL
OP0
RL & WL
Write-
only
OP<3:0>
0001_B: RL =3 /WL=1(default)
0010_B: RL =4 /WL=2
0011_B: RL =5 /WL=2
0100_B: RL =6 /WL=3
0101_B: RL =7 /WL=4
0110_B :RL =8 /WL=4
All others : reserved
MR3 I/O Configuration 1 (MA <7:0> =03H) :
OP7
OP6
OP5
(RFU)
OP4
OP3
OP2
OP1
DS
OP0
0000_B: reserved
0001_B: 34.3-ohm typical
0010_B: 40-ohm typical (default)
DS
Write-
only
0011_B: 48-ohm typical
OP<3:0> 0100_B: 60-ohm typical
0101_B: reserved for 68.6-ohm typical
0110_B :80-ohm typical
0111_B :120-ohm typical (optional)
All others : reserved
MR4 Device Temperature (MA <7:0> =04H) :
OP7 OP6 OP5
OP4
TUF
(RFU)
OP3
OP2 OP1 OP0
SDRAM Refresh Rate
000_B: SDRAM Low temperature operating limit exceeded
001_B: 4X t_REF, 4x t_REFlqb, 4x t_REFW
010_B: 2X t_REF, 2x t_REFlqb, 2x t_REFW
SDRAM Refresh Rate
Read-
only
OP<2:0>
011_B: 1X t_REF, 1x t_REFlqb, 1x t_REFW (≤85℃)
100_B: Reserved
101_B: 0.25X t_REF, 0.25x t_REFlqb, 0.25x t_REFW, do not de-rate
SDRAM AC timing
110_B :0.25X t_REF, 0.25x t_REFlqb, 0.25x t_REFW, de-rate SDRAM
AC timing
111_B :SDRAM High temperature operating limit exceeded
Temperature Update Flag
(TUF)
Read-
only
OP<7> ^{0B: OP<2:0> value has not changed since last read of MR4}
1_B: OP<2:0> value has changed since last read of MR4
NOTE 1 A Mode Register Read from MR4 will reset OP7 to ‘0’.
NOTE 2 OP7 is reset to ‘0’ at power-up. OP<2:0> bits are undefined after power-up.
Confidential
- 19/129 -
Rev.1.0 July 2016