AS4C64M16MD2-25BCN Datasheet, PDF (114/129 Pages) Alliance Semiconductor Corporation – Configurable Drive Strength

Parameter
DQ and DM input hold time
(VREF based)
DQ and DM input setup time
(VREF based)
DQ and DM input pulse width
Write command to first DQS
latching transition
DQS input high-level width
DQS input low-level width
DQS dalling edge to CK setup
time
DQS dalling edge hold time
from CK
Write postamble
Write preamble
Symbol
tDH
tDS
tDIPW
tDQSS
tDQSH
tDQSL
tDSS
tDSH
tWPST
tWPRE
min/ min
max tCK
min
min
min
min
max
min
min
min
min
min
min
Write Parameters^*14
AS4C64M16MD2-25BCN
AS4C32M32MD2-25BCN
LPDDR2
800
Unit
270
ps
270
0.35
tCK(avg)
0.75
tCK(avg)
1.25
0.4
tCK(avg)
0.4
tCK(avg)
0.2
tCK(avg)
0.2
tCK(avg)
0.4
tCK(avg)
0.35
tCK(avg)
Parameter
CKE min. pulse width (high
and low pulse width)
CKE input setup time
CKE input hold time
Address and control input
setup time (Vref based)
Address and control input
hold time (Vref based)
Address and control input
pulse width
Clock Cycle Time
CKE Input Setup Time
CKE Input Hold Time
Address & Control Input
Setup Time
Address & Control Input Hold
Time
DQS Output Data Access
Time from CK/CK#
Data Strobe Edge to Ouput
Data Edge tDQSQb - 1.2
tDQSQb max - 1.2 ns
Data Hold Skew Factor
MODE REGISTER Write
command period
Mode Register Read
command period
Symbol
tCKE
tISCKE ^*2
tIHCKE ^*3
tIS ^*1
tIH ^*1
tIPW
tCKb
tISCKEb
tIHCKEb
tISb
tIHb
tDQSCKb
tDQSQb
tQHSb
tMRW
tMRR
min/ min
max tCK
CKE Input parameters
LPDDR2
800
min 3
3
min
0.25
min
0.25
Command Address Input Parameters ^*14
min
290
min
290
min
0.4
Boot Parameters (10MHz - 55MHz) ^*8,10,11
max
100
-
min
18
min
-
2.5
min
-
2.5
min
-
1150
min
-
min
-
max
max -
1150
2
10.0
1.2
max -
1.2
Mode Register Parameters
min 5
5
min 2
2
Unit
tCK(avg)
tCK(avg)
tCK(avg)
ps
ps
tCK(avg)
ns
ns
ns
ps
ps
ps
ns
ns
ns
tCK(avg)
tCK(avg)
Confidential
- 114/129 -
Rev.1.0 July 2016