AKD4648-C Datasheet, PDF (9/71 Pages) Asahi Kasei Microsystems – stereo CODEC with MIC/HP/SPK amplifier

[AKD4648-C]
(4-3) All interface signals are fed externally
PORT3 (DSP) is used. Nothing should be connected to PORT1 (DIR) and PORT2 (DIT).
The system clock (PLL reference clock) should be connected to MCLK of PORT3.
In case of supplying MCKO to DSP, the JP14 (4115_MCKI)’s lower side should be connected to MCLK of DSP.
X’tal oscillator should be removed from X1.
The jumper pins should be set as the follows.
JP14
4115_MCKI
JP15
DIR_MCLK
JP16
BICK
JP20
JP2
SDTO_IN
RIN3 VCOC
JP17
LRCK
JP19
DIR_SEL
Slave Master
JP21
SDTI
DIR ADC
<KM088701>
-9-
2007/04