AKD4648-C Datasheet, PDF (6/71 Pages) Asahi Kasei Microsystems – stereo CODEC with MIC/HP/SPK amplifier

[AKD4648-C]
(3) PLL Slave Mode
(3-1) Reference Clock : MCKI pin
(3-1-1) Evaluation of A/D using DIT of AK4115
PORT2 (DIT) and PORT3 (DSP) are used. Nothing should be connected to PORT1 (DIR).
The system clock (PLL reference clock) should be connected to MCLK of PORT3. MCKO of AK4648 should be
input to AK4115’s XTI. X’tal oscillator should be removed from X1.
The jumper pins should be set as follows.
JP14
4115_MCKI
JP15
DIR_MCLK
JP16
BICK
JP17
LRCK
JP19
DIR_SEL
JP21
SDTI
JP20
JP2
SDTO_IN
Slave Master
DIR ADC
RIN3 VCOC
(3-1-2) Evaluation of Loop-back using AK4115
PORT2 (DIT) and PORT3 (DSP) are used. Nothing should be connected to PORT1 (DIR).
The system clock (PLL reference clock) should be connected to MCLK of PORT3. MCKO of AK4648 should be
input to AK4115’s XTI. X’tal oscillator should be removed from X1.
The jumper pins should be set as follows.
JP14
4115_MCKI
JP15
DIR_MCLK
JP16
BICK
JP17
LRCK
JP19
DIR_SEL
JP21
SDTI
JP20
JP2
SDTO_IN
Slave Master
DIR ADC
RIN3 VCOC
(3-1-3) All interface signals are fed externally
PORT3 (DSP) is used. Nothing should be connected to PORT1 (DIR) and PORT2 (DIT).
BICK and LRCK inputs should be synchronized with MCKO of AK4648.
MCLK (PLL reference clock), BICK, LRCK and SDTI are supplied from PORT3. The JP14 (4115_MCKI)’s
lower side (MCKO of AK4648) should be connected to MCLK of DSP.
The jumper pins should be set as follows.
JP14
4115_MCKI
JP15
DIR_MCLK
JP16
BICK
JP17
LRCK
JP19
DIR_SEL
JP21
SDTI
JP20
JP2
SDTO_IN
Slave Master
DIR ADC
RIN3 VCOC
<KM088701>
-6-
2007/04