AKD4121 Datasheet, PDF(9/35 Page) Asahi Kasei Microsystems

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AKD4121 Datasheet, PDF (9/35 Pages) Asahi Kasei Microsystems – AK4121 Evalation Board Rev.B

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ASAHI KASEI

[AKD4121]

2. Setting of fso (output fs) block

2-1. Optical Output(PORT4). Clocks are fed from AK4114 (DIT). (IIS Master Mode only.)

The X2(Xâtal) or external clock via PORT3 can be used as the system clock of the output block.

Please remove X2 when unused.

2-1-a. Jumper setting

Parts No.

Setting

JP5

DIT

OPEN: Using Xâtal on board

JP6

PORT3: Clock input form PORT3

(DIR: Using clock from DIR fo Bypass Mode)

JP7

SHORT

JP8

SHORT

JP9

SHORT

JP11

OPEN

Table 6. Jumper setting(Refer following figures)

JP5

DIT

JP6

JP8

JP9

JP7

JP11

PORT3

DIR

SRC-MCLK DIT-SOURCE

OBICK OLRCK

Using on-board Xâtal

ILRCK

10pin

Bypass

Output

JP5

DIT

JP6

JP8

JP9

JP7

JP11

PORT3

DIR

SRC-MCLK DIT-SOURCE

OBICK OLRCK

Using External Clock

Figure 8. Jumper setting

ILRCK

10pin

Bypass

Output

-9-

2004/08

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