AKD4121 Datasheet, PDF (19/35 Pages) Asahi Kasei Microsystems – AK4121 Evalation Board Rev.B

ASAHI KASEI
[AKD4121]
3-2-2. Clock are fed through the 10-pin port(PORT3)
3-2-2-a. Jumper setting
parts No.
JP8
JP9
JP7
JP5
JP6
JP11
X2
setting
OPEN
OPEN
OPEN
(don’t care)
OPEN
OPEN
(don’t care)
Table20. Jumper setting
JP5
DIT
JP6
JP8
JP9
PORT3
JP7
JP11
PORT3
SRC-MCLK
(don’t care)
DIR
DIT-SOURCE
OBICK
OLRCK
Figure 20. Jumper setting
ILRCK
10pin
Bypass
Output
3-2-2-b. Audio Interface Format
Mode
0
1
2
3
SW5-1 SW5-2
ODIF1 ODIF0
SDTO Format
OBICK (Master)
L
L
16bit LSB Justified
64fs
L
H
20bit LSB Justified
64fs
H
L
20bit MSB Justified
64fs
H
H
20bit I²S Compatible
64fs
Table 21. AK4121 Audio Interface Format setting
123
fso 1/2 MCLK
SW5
16bit, Right justified
123
fso 1/2 MCLK
SW5
20bit, Right justified
123
123
fso 1/2 MCLK
fso 1/2 MCLK
SW5
SW5
Left justified
I²S
Figure 21. DIP switch setting
<KM069301>
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2004/08