AKD4121 Datasheet, PDF (16/35 Pages) Asahi Kasei Microsystems – AK4121 Evalation Board Rev.B

ASAHI KASEI
3-1-2. All clock are fed through the 10-pin port
3-1-2-a. Jumper setting
Parts No.
Setting
JP1
OUT
JP2
OPEN
JP3
OPEN
JP4
OPEN
X1
(don’t care)
Table 16. Jumper setting(Refer following figures)
JP1
JP2
JP3
JP4
OUT
IN
IMCLK
IBICK
SDTI
ILRCK
Figure 16. Jumper setting
3-1-2-b. Audio Interface Format
Audio Interface
Format
SW3-1
DIF2
SRC:AK4121
SW3-2
DIF1
16bit, Right justified
0
0
20bit, Right justified
0
0
Left justified
0
1
I²S
0
1
24bit, Right justified
1
0
Table 17. DIP switch (SW3) setting
SW3-3
DIF0
0
1
0
1
0
[AKD4121]
12345
fsi-DIR 1/2MCLK
SW3
16bit, Right justified
12345
fsi-DIR 1/2MCLK
SW3
20bit, Right justified
<KM069301>
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2004/08