AK8180C Datasheet, PDF (9/12 Pages) Asahi Kasei Microsystems – 2.5V, 3.3V LVCMOS 1:12 Clock Fanout Buffer

Function Table
The following table shows the inputs/outputs clock state configured through the control pins.
AK8180C
Control Pin
CLK_SEL
OE
CLK_STOP
Table 1: Control-Pin-Setting Function Table
Default
0
1 PCLK differential input selected
1
CCLK input selected
1 Outputs disabled.(High impedance) Outputs enabled
1 ^{Outputs synchronously stopped in} Outputs active
logic low state.
Application example of CLK_STOP
MS1305-E-00
-9 -
May-2011