AK8180C Datasheet, PDF (5/12 Pages) Asahi Kasei Microsystems – 2.5V, 3.3V LVCMOS 1:12 Clock Fanout Buffer

AK8180C
Power Supply Current <3.3V>
VDD= 3.3V5%, Ta: -40 to +85℃
Parameter
Symbol
Conditions
Min
Typ
Full operation ⁽¹⁾
CCLK0=350MHz
IDD1 _{CLK_SEL=L}
155
Quiescent state ⁽¹⁾⁽²⁾
IDD2
1.0
(1) The outputs have no loads. (2) All inputs are in default state by the internal pull up/down resisters.
Max Unit
175 mA
2.0 mA
DC Characteristics <3.3V>
All specifications at VDD= 3.3V5%, Ta: -40 to +85℃, unless otherwise noted
Parameter
Symbol
Conditions
MIN
TYP
MAX Unit
High Level Input Voltage
Low Level Input Voltage
Peak-to-Peak Input Voltage
Common Mode Range ⁽¹⁾
Input Current ⁽²⁾
High Level Output Voltage
Low Level Output Voltage
Output Impedance
VIH
VIL
Vpp
Vcmr
IL1
VOH
VOL
LVCMOS
LVCMOS
LVPECL
LCPECL
Vin=GND or VDD
IOH= -24mA ⁽³⁾
IOL= +24mA ⁽³⁾
IOL= +12mA
2.0
-0.3
250
1.1
-300
2.4
VDD+0.3 V
0.8
V
mV
VDD-0.6 V
+300 μA
V
0.55
V
0.30
17

(1) Vcmr(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the
Vcmr range and the input swing lies within the Vpp(DC) specification.
(2) Input pull-up / pull down resistors influence input current.
(3) The AK8180C is capable of driving 50  transmission lines of the incident edge. Each output drives one 50  parallel
terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50  series
terminated transmission lines(for VDD=3.3V) or one 50  series terminated transmission line(for VDD=2.5V).
AC Characteristics <3.3V> ⁽¹⁾
All specifications at VDD= 3.3V5%, Ta: -40 to +85℃, unless otherwise noted
Parameter
Symbol
Conditions
MIN
TYP
MAX Unit
Input Frequency
fIN
Pin: CCLK, PCLKp/n
0
350 MHz
Input Pulse Width
tpwIN
Pin: CCLK, PCLKp/n
1.4
ns
Peak-to-Peak Input Voltage Vpp
Pin: PCLKp/n
400
Common Mode Range ⁽²⁾ Vcmr Pin: PCLKp/n
1.3
Input Rise/Fall time ⁽³⁾
trIN,tfOUT Pin: CCLK 0.8 to 2.0V
1000 mV
VDD-0.8
1.0
ns
Output Frequency
fOUT
Pin: Q0-11
0
350 MHz
Propagation Delay
Output Disable Time
Output Enable Time
Setup Time
tPLH
tPHL
tPLZ,tPHZ
tPZL,tPZH
tS
PCLK to any Q
CCLK to any Q
CCLK to CLK_STOP
PCLK to CLK_STOP
1.0
1.8
3.0
ns
0.8
1.6
2.8
11
ns
11
ns
0.0
ns
0.0
CCLK to CLK_STOP
1.0
Hold Time
tH
PCLK to CLK_STOP
1.5
ns
Output-to-Output Skew
Device-to-Device Skew
Output Pulse Skew ⁽⁴⁾
tsk(O)
tskPP
tsk(P)
CCLK
PCLK
150 ps
2.0
ns
300
ps
400
Output Duty Cycle
DCOUT fOUT < 170MHz DCREF =50%
45
50
55
%
Output Rise/Fall Time
tr, tf
0.55 to 2.4V
0.1
1.0
ns
MS1305-E-00
-5 -
May-2011