AK8180C Datasheet, PDF (7/12 Pages) Asahi Kasei Microsystems – 2.5V, 3.3V LVCMOS 1:12 Clock Fanout Buffer

AK8180C
Parameter
Symbol
Conditions
MIN
TYP
MAX Unit
CCLK to CLK_STOP
0.0
Setup Time
tS
PCLK to CLK_STOP
0.0
ns
CCLK to CLK_STOP
1.0
Hold Time
tH
PCLK to CLK_STOP
1.5
ns
Output-to-Output Skew
tsk(O)
150 ps
Device-to-Device Skew
Output Pulse Skew ⁽⁴⁾
tskPP
tsk(P)
CCLK
PCLK
2.7
ns
200
ps
300
Output Duty Cycle
DCOUT DCREF =50%
45
50
55
%
Output Rise/Fall Time
tr, tf
0.6 to 1.8V
0.1
1.0
ns
(1) AC characteristics apply for parallel output termination of 50  to VTT.
(2) Vcmr(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained wh en the crosspoint is within
the Vcmr range and the input swing lies within the Vpp(AC) specification. Violation of Vcmr or Vpp impacts tPLH/PHL and tskD.
(3) Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation dela y, device-to-device skew,
input pulse width, output duty cycle and maximum frequency specifications.
(4) Output pulse skew tskO is the absolute difference of the propagation delay times:| tPLH - tPHL |.
Figure 1 CCLK AC Test Reference
Figure 2 PCLK AC Test Reference
MS1305-E-00
-7 -
May-2011