AK8180A Datasheet, PDF (9/12 Pages) Asahi Kasei Microsystems – 2.5V, 3.3V LVCMOS 1:10 Clock Fanout Buffer

Function Table
The following table shows the inputs/outputs clock state configured through the control pins.
AK8180A
Control Pin
CCLK_SEL
Table 1: Control-Pin-Setting Function Table
Default
0
0
CCLK0
1
CCLK1
DSELA
0
QA0-2 = REFCLK x 1
QA0-2 = REFCLK x 1/2
DSELB
0
QB0-2 = REFCLK x 1
QB0-2 = REFCLK x 1/2
DSELC
0
QC0-3 = REFCLK x 1
MR/ OE
0
Output enabled
REFCLK is the selected input clock through the CCLK_SEL pin.
QC0-3 = REFCLK x 1/2
Internal reset. Outputs disabled.
(High impedance)
MS1281-E-00
-9-
Mar-2011