AK8180A Datasheet, PDF (5/12 Pages) Asahi Kasei Microsystems – 2.5V, 3.3V LVCMOS 1:10 Clock Fanout Buffer

AK8180A
Power Supply Current <3.3V>
VDD=VDDA=VDDB=VDDC= 3.3V±5%, Ta: -40 to +85℃
Parameter
Full operation ⁽¹⁾
Quiescent state ⁽¹⁾
Symbol
IDD1
IDD2
Conditions
CCLK0=250MHz
CCLK1=H
CCLK0=H
CCLK1=H
Min
Typ
Max Unit
84
105 mA
0.8
1.7 mA
(1) The outputs have no loads. CCLK_SEL=L, DSELA=DSELB=DSELC=L, MR/OE =L
DC Characteristics <3.3V>
All specifications at VDD=VDDA=VDDB=VDDC= 3.3V±5%, Ta: -40 to +85℃, unless otherwise noted
Parameter
Symbol
Conditions
MIN
TYP
MAX Unit
High Level Input Voltage
VIH
LVCMOS
2.0
VDD+0.3 V
Low Level Input Voltage
Input Current ⁽¹⁾
High Level Output Voltage
Low level Output Voltage
VIL
LVCMOS
IL1 Vin=GND or VDD
VOH
IOH= -24mA ⁽²⁾
VOL
IOL= +24mA ⁽²⁾
IOL= +12mA
-0.3
-200
2.4
0.8
V
+200 μA
V
0.55
0.30
V
Output Impedance
ZOUT
14-17
W
(1) Input pull-up / pull down resistors influence input current.
(2) The AK8180A is capable of driving 50 W transmission lines of the incident edge. Each output drives one 50 W parallel
terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 W series
terminated transmission lines.
AC Characteristics <3.3V> ⁽¹⁾
All specifications at VDD=VDDA=VDDB=VDDC= 3.3V±5%, Ta: -40 to +85℃, unless otherwise noted
Parameter
Symbol
Conditions
MIN
TYP MAX Unit
Input Frequency ⁽²⁾
fIN
CCLK0,1
250 MHz
Input Pulse Width
tpwIN
CCLK0,1
1.4
ns
Input Rise/Fall time ⁽³⁾
trIN,tfOUT CCLK0,1 0.8 to 2.0V
1.0
ns
Output Frequency ⁽²⁾
fOUT
DSELA,B,C= 0 x1 output
DSELA,B,C= 1 x1/2 output
250
125
MHz
Propagation Delay
tPLH
CCLK0,1 to any Q
tPHL
CCLK0,1 to any Q
1.15
1.15
2.0
2.0
3.4
3.4
ns
Output Disable Time
tPLZ,tPHZ
10
ns
Output Enable Time
tPZL,tPZH
10
ns
Within one bank
150
Output-to-Output Skew
tsk(O)
Any output, same output divider
Any output, Any output divider
200 ps
350
Device-to-Device Skew
Output Pulse Skew ⁽⁴⁾
tskPP
tsk(P)
2.25 ns
200 ps
Output Duty Cycle ⁽⁵⁾
DCOUT
DCREF= 50%
x1 output
DCREF= 25-75% x1/2 output
45
47
50
50
55
53
%
Output Rise/Fall Time
tr, tf
0.55 to 2.4V
0.1
1.0
ns
(1) AC characteristics apply for parallel output termination of 50 W to VTT.
(2) The AK8180A is functional up to an input and output clock frequency of 350MHz and is characterized up to 250MHz.
(3) Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew,
input pulse width, output duty cycle and maximum frequency specifications.
(4) Output pulse skew tskO is the absolute difference of the propagation delay times:| tPLH - tPHL |.
(5) Output duty cycle is frequency dependent (= 0.5 ± tskO x fout). For example at fout = 125 MHz the output duty
cycle limit is 50% ± 2.5%.
MS1281-E-00
-5-
Mar-2011