AK5355 Datasheet, PDF (9/14 Pages) Asahi Kasei Microsystems – LOW POWER 16BIT ADC

ASAHI KASEI
[AK5355]
„ Digital High Pass Filter
The AK5355 has a Digital High Pass Filter (HPF) to cancel DC-offset in both the ADC and input gain amplifier. The
cut-off frequency of the HPF is 3.4Hz at fs=44.1kHz. This cut-off frequency scales with the sampling frequency (fs).
„ Input Gain Amplifier
The AK5355 includes an input gain amplifier. The gain can be changed to 0dB or +15dB by using the SEL pin. Input
impedance is 40kΩ typically.
„ Power down
SEL pin
Gain
L
0dB
H
+15dB
Table 2. Input Gain Amplifier
The AK5355 is placed in the power-down mode by bringing PDN “L”. The digital filter is also reset at the same time. This
reset should always be done after power-up. An analog initialization cycle starts after exiting the power-down mode. The
output data SDTO becomes available after 4128 cycles of LRCK clock. During initialization, the ADC digital data outputs
of both channels are forced to a 2’s complement “0”. The ADC outputs settle to the data corresponding to the input signals
at the end of initialization (Settling time equals the group delay time approximately).
PDN
Internal
State
A/D In
(Analog)
A/D Out
(Digital)
Clock In
MCLK,LRCK,BCLK
4128/fs(93.6ms@fs=44.1kHz)
Normal Operation
GD ₍₁₎
Power-down
Idle Noise
(2)
“0”data
(3)
Initialize
Normal Operation
GD
“0”data
Idle Noise
Notes:
(1) Digital output corresponding to the analog input is delayed by the Group Delay amount (GD).
(2) A/D output is “0” data in the power-down state.
(3) When the external clocks (MCLK, BCLK and LRCK) are stopped, the AK5355 should be placed in the power-
down state.
„ System Reset
Figure 6. Power-down/up sequence example
The AK5355 should be reset once by bringing PDN ”L” upon power-up. The AK5355 is powered up and the internal
timing starts clocking by LRCK “↑” after exiting reset and power down state by MCLK. The AK5355 is in the power-down
mode until MCLK and LRCK are input.
MS0113-E-00
-9-
2001/08