AK5355 Datasheet, PDF (6/14 Pages) Asahi Kasei Microsystems – LOW POWER 16BIT ADC

ASAHI KASEI
[AK5355]
SWITCHING CHARACTERISTICS
(Ta=25°C; VA, VD=2.1 ∼ 3.6V; C_L=20pF)
Parameter
Symbol
min
typ
Control Clock Frequency
Master Clock (MCLK)
256fs: Frequency
fCLK
2.048
11.2896
Pulse Width Low
Pulse Width High
384fs: Frequency
tCLKL
tCLKH
fCLK
28
28
3.072
16.9344
Pulse Width Low
tCLKL
23
Pulse Width High
512fs: Frequency
Pulse Width Low
tCLKH
fCLK
tCLKL
23
4.096
16
22.5792
Pulse Width High
tCLKH
16
Channel Clock (LRCK) Frequency
fs
8
44.1
Duty Cycle
duty
45
Audio Interface Timing
BCLK Period
tBLK
312.5
BCLK Pulse Width Low
tBLKL
130
Pulse Width High
BCLK “↓” to LRCK
LRCK Edge to SDTO (MSB)
BCLK “↓” to SDTO
tBLKH
tBLR
tDLR
tDSS
130
-tBLKH+50
Reset / Initializing Timing
PDN Pulse Width
tPW
150
PDN “↑” to SDTO
(Note 8)
tPWV
4128
Note 8. This is the number of LRCK rising after the PDN pin is pulled high.
max
12.8
19.2
25.6
50
55
tBLKL-50
80
80
Units
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
kHz
%
ns
ns
ns
ns
ns
ns
ns
1/fs
MS0113-E-00
-6-
2001/08