AK5355 Datasheet, PDF (8/14 Pages) Asahi Kasei Microsystems – LOW POWER 16BIT ADC

ASAHI KASEI
[AK5355]
OPERATION OVERVIEW
„ System Clock
The clocks required to operate are MCLK (256fs/384fs/512fs), LRCK (fs) and BCLK (32fs∼). The master clock (MCLK)
should be synchronized with LRCK. The phase between these clocks does not matter. The frequency of MCLK can be
input as 256fs, 384fs or 512fs. When the 384fs or 512fs is input, the internal master clock is divided into 2/3 or 1/2
automatically.
*fs is sampling frequency.
All external clocks (MCLK, BCLK and LRCK) should always be present whenever the ADC is in operation. If these
clocks are not provided, the AK5355 may draw excess current and will not operate properly because it utilizes these clocks
for internal dynamic refresh of registers. If the external clocks are not present, the AK5355 should be placed in power-
down mode.
„ Audio Data I/F Format
The SDTO, BCLK and LRCK pins are connected to an external controller. The audio data format has two modes, MSB-
first and 2’s compliment. The data format is set using the DIF pin.
No. DIF pin SDTO (ADC)
LRCK
0
L
16bit MSB justified Lch: “H”, Rch: “L”
1
H
I²S Compatible
Lch: “L”, Rch: “H”
Table 1. Audio Data Format
BCLK
≥ 32fs
≥ 32fs
Figure
Figure 4
Figure 5
LRCK
0 1 23
BCLK(32fs)
8 9 10 11 12 13 14 15 0 1
23
8 9 10 11 12 13 14 15 0 1
SDTO(o)
15 14 13 8 7 6 5 4 3 2 1 0 15 14 13 8 7 6 5 4 3 2 1 0 15
0 1 23
BCLK(64fs)
14 15 16 17 18
31 0 1 2 3
14 15 16 17 18
SDTO(o)
15 14 13 13 2 1 0
15 14 13 1 2 1 0
15:MSB, 0:LSB
Lch Data
Figure 4. Audio Data Timing (No.0)
Rch Data
31 0 1
15
LRCK
0 1 23 4
BCLK(32fs)
9 10 11 12 13 14 15 0 1 2 3 4
9 10 11 12 13 14 15 0 1
SDTO(o)
0 15 14 13 7 7 6 5 4 3 2 1 0 15 14 13 7 7 6 5 4 3 2 1 0
0 1 23 4
BCLK(64fs)
14 15 16 17 18
31 0 1 2 3 4 14 15 16 17 18
SDTO(o)
15 14 13
210
15 14 13 2 2 1 0
15:MSB, 0:LSB
Lch Data
Figure 5. Audio Data Timing (No. 1)
Rch Data
31 0 1
MS0113-E-00
-8-
2001/08