AK4421 Datasheet, PDF(9/19 Page) Asahi Kasei Microsystems – 192kHz 24-Bit Stereo ΔΣ DAC with 2Vrms Output

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

AK4421 Datasheet, PDF (9/19 Pages) Asahi Kasei Microsystems – 192kHz 24-Bit Stereo ΔΣ DAC with 2Vrms Output

◁

[AK4421]

OPERATION OVERVIEW

â System Clock

The external clocks required to operate the AK4421 are MCLK, LRCK, and BICK. The master clock (MCLK) should be

synchronized with LRCK, but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the

delta-sigma modulator. Sampling speed and MCLK frequency are detected automatically, and then the internal master

clock is set to the appropriate frequency (Table 1).

The AK4421 is automatically placed in power saving mode when MCLK and LRCK stop during normal operation mode,

and the analog output goes to 0V(typ). When MCLK and LRCK are input again, the AK4421 is powered up. After exiting

reset following power-up, the AK4421 is not fully operational until MCLK and LRCK are input.

LRCK

32.0kHz

44.1kHz

48.0kHz

88.2kHz

96.0kHz

176.4kHz

192.0kHz

128fs

22.5792

24.5760

192fs

33.8688

36.8640

MCLK (MHz)

256fs

384fs

512fs

16.3840

22.5792

24.5760

22.5792 33.8688

24.5760 36.8640

768fs

24.5760

33.8688

36.8640

1152fs

36.8640

Sampling

Speed

Normal

Double

Quad

Table 1. System Clock Example

When MCLK= 256fs/384fs, the Auto Setting Mode supports sampling rate of 32kHz~96kHz (Table 1). But, when the

sampling rate is 32kHz~48kHz, DR and S/N will degrade by approximately 3dB as compared to when MCLK=

512fs/768fs (Table 2).

MCLK

DR,S/N

256fs/384fs

99dB

512fs/768fs

102dB

Table 2. Relationship between MCLK frequency and DR, S/N (fs= 44.1kHz)

â Audio Serial Interface Format

The audio data is shifted in via the SDTI pin using the BICK and LRCK inputs. The DIF pin can select between two serial

data modes as shown in Table 3. In all modes the serial data is MSB-first, twoâs complement format and it is latched on

the rising edge of BICK. In one cycle of LRCK, eight âHâ pulses or more must not be input to the DIF pin.

Mode DIF SDTI Format

L 24bit MSB justified

H 24bit I2S

BICK

â¥48fs

Table 3. Audio Data Formats

Figure

Figure 3

Figure 4

MS0945-E-01

-9-

2008/08

▷