AK5393 Datasheet, PDF (8/18 Pages) Asahi Kasei Microsystems – Enhanced Dual bit 96 kHz 24-bit ADC

ASAHI KASEI
[AK5393]
DIGITAL CHARACTERISTICS
(Ta=25°C; VA=5.0V±5%; VD=3.0 ~ 5.25V)
Parameter
Symbol
min
High-Level Input Voltage
VIH
70%VD
Low-Level Input Voltage
VIL
-
High-Level Output Voltage Iout=-20µA
VOH
VD-0.1
Low-Level Output Voltage Iout=20µA
VOL
-
Input Leakage Current
Iin
-
typ
max
Units
-
-
V
-
30%VD
V
-
-
V
0.1
V
-
±10
µA
SWITCHING CHARACTERISTICS
(Ta=25°C; VA=5.0V±5%; VD=3.0 ~ 5.25V; C_L=20pF)
Parameter
Symbol min
Control Clock Frequency
Master Clock
256fs:
Pulse width Low
Pulse width High
Serial Data Output Clock (SCLK)
Channel Select Clock (LRCK)
duty cycle
fCLK
tCLKL
tCLKH
fSLK
fs
0.256
29
29
1
25
Serial Interface Timing
(Note 9)
Slave Mode(SMODE1="L")
SCLK Period
SCLK Pulse width Low
Pulse width High
SCLK falling to LRCK Edge (Note 10)
LRCK Edge to SDATA MSB Valid
SCLK falling to SDATA Valid
SCLK falling to FSYNC Edge
Master Mode(SMODE1="H")
SCLK Frequency (DFS="L")
SCLK Frequency (DFS="H")
duty cycle
FSYNC Frequency
duty cycle
SCLK falling to LRCK Edge
LRCK Edge to FSYNC rising
SCLK falling to SDATA Valid
SCLK falling to FSYNC Edge
tSLK
tSLKL
tSLKH
tSLR
tDLR
tDSS
tSF
144.7
65
65
-45
-45
fSLK
fSLK
fFSYNC
tSLR
-20
tLRF
tDSS
tSF
-20
Reset/Calibration timing
RST Pulse width
RST falling to CAL rising
RST rising to CAL falling (Note 11)
RST rising to SDATA Valid (Note 11)
tRTW
150
tRCR
tRCF
tRTV
typ
12.288
6.144
48
128fs
64fs
50
2fs
50
1
8704
8960
max
13.824
6.912
108
75
45
45
45
45
20
45
20
50
Units
MHz
ns
ns
MHz
kHz
%
ns
ns
ns
ns
ns
ns
ns
Hz
Hz
%
Hz
%
ns
tslk
ns
ns
ns
ns
1/fs
1/fs
Notes: 9. Refer to Serial Data interface.
10. Specified LRCK edges not to coincide with the rising edges of SCLK.
11. The number of the LRCK rising edges after RST brought high at DFS="L". The value is in master mode.
In slave mode it becomes one LRCK clock(1/fs) longer. When DFS="H", tRCF=17408 and tRTV=17920.
M0038-E-04
-8-
2000/4