AK5393 Datasheet, PDF (14/18 Pages) Asahi Kasei Microsystems – Enhanced Dual bit 96 kHz 24-bit ADC

ASAHI KASEI
[AK5393]
SYSTEM DESIGN
Figure 5 and 6 show the system connection diagram. An evaluation board[AKD5393] is available which demonstrates
the optimum layout, power supply arrangements and measurement results.
+3.3~5V
Digital
Reset &
Cal Control
Mode
Select
System
Controller
256fs@fs=48k
System Ground
Lch+
Lch-
+
10µ
10µ 0.1µ
+
1
2
0.22µ
3
VREFL
GNDL
VCOML
VREFR 28
0.1µ
GNDR 27
0.22µ
VCOMR 26
+
10µ
4 AINL+
5 AINL-
6 ZCAL
AK5393
AINR+ ²⁵
AINR- 24
VA 23
7 VD
0.1µ
8 DGND
AGND 22
BGND 21
Rch+
Rch-
0.1µ
+10µ
9 CAL
TEST 20
10 ^RST
HPFE 19
11 SMODE2
DFS 18
12 SMODE1
fs
13 LRCK
MCLK 17
FSYNC 16
14 SCLK
SDATA 15
+5V
Analog
Analog Ground
Figure 5. Typical Connection Diagram
Notes:
- LRCK = fs, SCLK=64fs.
- Power lines of VA and VD should be distributed separately from the point
with low impedance of regulator etc.
- GND, BGND and DGND must be connected to the same analog ground plane.
- All input pins except pull-down/pull-up pins should not be left floating.
Digital Ground
System
Controller
Analog Ground
1 VREFL
VREFR 28
2 GNDL
GNDR 27
3 VCOML
VCOMR 26
4 AINL+
5 AINL-
6 ZCAL
AK5393
AINR+ ²⁵
AINR- 24
VA 23
7 VD
AGND 22
8 DGND
BGND 21
9 CAL
10 ^RST
TEST 20
HPFE 19
11 SMODE2
DFS 18
12 SMODE1
MCLK 17
13 LRCK
FSYNC 16
14 SCLK
SDATA 15
Figure 6 Ground layout
M0038-E-04
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