AK5381 Datasheet, PDF (8/20 Pages) Asahi Kasei Microsystems – 24Bit 96kHz ΔΣ ADC

ASAHI KASEI
SWITCHING CHARACTERISTICS (fs=4kHz ∼ 48kHz)
(Ta=Tmin ∼ Tmax; VA=4.5 ∼ 5.5V; VD=2.7 ∼ 5.5V; C_L=20pF)
Parameter
Symbol
min
typ
Master Clock Timing
Frequency
Pulse Width Low
Pulse Width High
fCLK
tCLKL
tCLKH
1.024
0.4/fCLK
0.4/fCLK
LRCK Frequency
fs
4
Duty Cycle
Slave mode
Master mode
45
50
Audio Interface Timing
Slave mode
SCLK Period
SCLK Pulse Width Low
Pulse Width High
LRCK Edge to SCLK “↑” (Note 9)
SCLK “↑” to LRCK Edge (Note 9)
LRCK to SDTO (MSB) (Except I²S mode)
SCLK “↓” to SDTO
tSCK
160
tSCKL
65
tSCKH
65
tLRSH
30
tSHLR
30
tLRS
tSSD
Master mode
SCLK Frequency
SCLK Duty
SCLK “↓” to LRCK
SCLK “↓” to SDTO
fSCK
64fs
dSCK
50
tMSLR
−20
tSSD
Reset Timing
PDN Pulse Width
(Note 10)
tPD
150
PDN “↑” to SDTO valid at Slave Mode (Note 11) ^tPDV
PDN “↑” to SDTO valid at Master Mode (Note 11) ^tPDV
4132
4129
Note 9. SCLK rising edge must not occur at the same time as LRCK edge.
Note 10. The AK5381 can be reset by bringing the PDN pin = “L”.
Note 11. This cycle is the number of LRCK rising edges from the PDN pin = “H”.
[AK5381]
max
Units
36.864
48
55
MHz
ns
ns
kHz
%
%
ns
ns
ns
ns
ns
35
ns
35
ns
Hz
%
20
ns
35
ns
ns
1/fs
1/fs
MS0200-E-02
-8-
2006/01