AK5381 Datasheet, PDF (15/20 Pages) Asahi Kasei Microsystems – 24Bit 96kHz ΔΣ ADC

ASAHI KASEI
[AK5381]
SYSTEM DESIGN
Figure 4 shows the system connection diagram. An evaluation board is available which demonstrates application circuits,
the optimum layout, power supply arrangements and measurement results.
Rch In
Lch In
Analog 5V
10u+
1 AINR
CKS0 16
+
2
10u
3
2.2u 0.1u
+
4
5
AINL
CKS2 15
CKS1
DIF 14
VCOM
PDN 13
AK5381
AGND
SCLK 12
+
10u
10u+
6 VA
0.1u
7 VD
8 DGND
0.1u
MCLK 11
LRCK 10
SDTO 9
Analog Ground
Mode
Control
Reset
Audio
Controller
System Ground
Note:
- AGND and DGND of the AK5381 should be distributed separately from the ground of external digital
devices (MPU, DSP etc.).
- All input pins except pull-down pin should not be left floating.
- The CKS1 pin should be connected VA or AGND.
Figure 4. Typical Connection Diagram
Digital Ground
Analog Ground
System
Controller
1 AINR
CKS0 16
2 AINL
CKS2 15
3 CKS1
DIF 14
4 VCOM _AK5381 PDN 13
5 AGND
SCLK 12
6 VA
MCLK 11
7 VD
LRCK 10
8 DGND
SDTO 9
Figure 5. Ground Layout
Note:
- AGND and DGND must be connected to the same analog ground plane.
MS0200-E-02
- 15 -
2006/01