AK5381 Datasheet, PDF (12/20 Pages) Asahi Kasei Microsystems – 24Bit 96kHz ΔΣ ADC

ASAHI KASEI
[AK5381]
OPERATION OVERVIEW
„ System Clock
MCLK (256fs/384fs/512fs), SCLK and LRCK (fs) clocks are required in slave mode. The LRCK clock input must be
synchronized with MCLK, however the phase is not critical. Table 1 shows the relationship of typical sampling frequency
and the system clock frequency. MCLK frequency, SCLK frequency, HPF (ON or OFF), the input level (CMOS or TTL)
and master/slave are selected by CKS2-0 pins as shown in Table 2.
All external clocks (MCLK, SCLK and LRCK) must be present unless PDN pin = “L”. If these clocks are not provided,
the AK5381 may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not
present, place the AK5381 in power-down mode (PDN pin = “L”). In master mode, the master clock (MCLK) must be
provided unless PDN pin = “L”.
fs
32kHz
44.1kHz
48kHz
96kHz
MCLK
256fs
384fs
512fs
8.192MHz 12.288MHz 16.384MHz
11.2896MHz 16.9344MHz 22.5792MHz
12.288MHz 18.432MHz 24.576MHz
24.576MHz 36.864MHz
N/A
Table 1. System Clock Example
768fs
24.576MHz
33.8688MHz
36.864MHz
N/A
CKS2
L
L
L
L
H
H
H
H
CKS1
L
L
H
H
L
L
H
H
CKS0
L
H
L
H
L
H
L
H
Input Level
CMOS
CMOS
CMOS
CMOS
TTL*
CMOS
CMOS
HPF Master/Slave
MCLK
ON
Slave
256/384fs (∼ 96kHz)
512/768fs (∼ 48kHz)
OFF
Slave
256/384fs (∼ 96kHz)
512/768fs (∼ 48kHz)
ON
Master
256fs (∼ 96kHz)
ON
Master
512fs (∼ 48kHz)
ON
Slave
256fs/384/512/768fs
(∼ 48kHz)
Reserved
ON
Master
384fs (∼ 96kHz)
ON
Master
768fs (∼ 48kHz)
Table 2. Mode Select
SCLK
≥ 48fs or 32fs
≥ 48fs or 32fs
64fs
64fs
≥ 48fs or 32fs
64fs
64fs
Note: SDTO outputs 16bit data at SCLK=32fs.
Note: The AK5381 does not support TTL interface at 96kHz.
„ Audio Interface Format
Two kinds of data formats can be chosen with the DIF pin (Table 3). In both modes, the serial data is in MSB first, 2’s
compliment format. The SDTO is clocked out on the falling edge of SCLK. The audio interface supports both master and
slave modes. In master mode, SCLK and LRCK are output with the SCLK frequency fixed to 64fs and the LRCK
frequency fixed to 1fs.
Mode
0
1
DIF pin
L
H
SDTO
LRCK
SCLK
24bit, MSB justified H/L ≥ 48fs or 32fs
24bit, I²S Compatible L/H ≥ 48fs or 32fs
Table 3. Audio Interface Format
Figure
Figure 1
Figure 2
MS0200-E-02
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2006/01