AK4550 Datasheet, PDF (8/15 Pages) Asahi Kasei Microsystems – LOW POWER & SMALL PACKAGE 16BIT CODEC

ASAHI KASEI
[AK4550]
OPERATION OVERVIEW
n System Clock Input
The AK4550 can be input MCLK=256fs, 384fs or 512fs. The input clock applied to the MCLK as internal master clock
is divided into 256fs automatically. The relationship between the external clock applied to the MCLK input and the
desired sample rate is defined in Table 1. The LRCK clock input must be synchronized with MCLK, however the phase
is not critical. *fs is sampling frequency.
When the synchronization is out of phase by changing the clock frequencies during normal operation, the AK4550 may
occur click noise. In case of DAC, click noise is avoided by setting the inputs to “0”.
All external clocks(MCLK, SCLK, LRCK) must be present unless PWAD and PWDA = ”L”. If these clocks are not
provided, the AK4550 may draw excess current and may not possibly operate properly because the device utilizes
dynamic refreshed logic internally.
fs
32.0kHz
44.1kHz
48.0kHz
256fs
8.1920MHz
11.2896MHz
12.2880MHz
MCLK
384fs
12.2880MHz
16.9344MHz
18.4320MHz
512fs
16.3840MHz
22.5792MHz
24.5760MHz
SCLK
32fs
64fs
1.0240MHz 2.048MHz
1.4112MHz 2.822MHz
1.5360MHz 3.072MHz
Table 1. System Clock Example
n Audio Serial Interface Format
Data is shifted in/out the SDTI/SDTO pins using SCLK and LRCK inputs. The data is MSB first, 2’s compliment.
LRCK
SCLK(i)
(32fs)
SDTI(i)
SDTO(o)
SCLK(i)
(64fs)
01
15 14
01
SDTO(o) _{15 14}
10 11 12 13 14 15 0 1
6 5 4 3 2 1 0 15 14
14 15 16 17
31 0 1
210
15 14
10 11 12 13 14 15 0 1
6 5 4 3 2 1 0 15 14
14 15 16 17
31 0 1
210
15 14
SDTI(i)
Don’t care
15 14
0 Don’t care
15 14
0
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 1. Audio Interface Timing
M0068-E-01
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2000/4