AK4550 Datasheet, PDF (6/15 Pages) Asahi Kasei Microsystems – LOW POWER & SMALL PACKAGE 16BIT CODEC

ASAHI KASEI
[AK4550]
SWITCHING CHARACTERISTICS
(Ta=25°C; VDD=2.3 ∼ 3.6V; C_L=20pF)
Parameter
Symbol
min
typ
max
Units
Master Clock Timing 256fs:
fCLK
2.048
11.2896
12.8
MHz
Pulse Width Low
tCLKL
28
ns
Pulse Width High
tCLKH
28
ns
384fs:
fCLK
3.072
16.9344
19.2
MHz
Pulse Width Low
tCLKL
23
ns
Pulse Width High
tCLKH
23
ns
512fs:
fCLK
4.096
22.5792
25.6
MHz
Pulse Width Low
tCLKL
16
ns
Pulse Width High
tCLKH
16
ns
LRCK Frequency
Duty Cycle
fs
8
44.1
50
kHz
45
55
%
Serial Interface Timing
SCLK Period
tSCK
312.5
ns
SCLK Pulse Width Low
tSCKL
130
ns
Pulse Width High
tSCKH
130
ns
LRCK Edge to SCLK “↑”
(Note 9)
tLRS
50
SCLK “↑” to LRCK Edge
(Note 9)
tSLR
50
LRCK Edge to SDTO (MSB)
tDLR
SCLK “↓” to SDTO
tDSS
SDTI Hold Time
tSDH
50
SDTI Setup Time
tSDS
50
ns
ns
80
ns
80
ns
ns
ns
Reset Timing
PWAD or PWDA Pulse Width
tPW
150
ns
PWAD ”↑” to SDTO Valid (Note 10)
tPWV
2081
1/fs
Notes: 9. SCLK rising edge must not occur at the same time as LRCK edge.
10. These cycles are the number of LRCK rising from PWAD rising.
M0068-E-01
-6-
2000/4