AK2306 Datasheet, PDF (8/38 Pages) Asahi Kasei Microsystems – Dual PCM CODEC for ISDN/VoIP TERMINAL ADAPTER

ASAHI KASEI
[AK2306/LV]
CIRCUIT DESCRIPTION
Block
AMPT0,1
AMPR0,1
AAF
A/D
D/A
SMF
BGREF
RING TONE
GENERATOR
GA0T/R
GA1T/R
GATN
SERIAL I/F
PLL
PCM I/F
Function
Op-amp for input gain adjustment. This op-amp has differential inputs.
Adjusting the gain with external resistors. The resistor larger than 10kΩ is
recommended for the feedback resistor.
<NOTE>
AMPT0(1) becomes automatically power down, when CODEC ch0(1) is power
down.
Op-amp for output gain adjustment. This op-amp is used as an inverting
amplifier. Adjusting the gain with external resistors. The resistor larger than
10kΩ is recommended for the feedback resistor.
Integrated anti-aliasing filter which prevents signals around the sampling rate
from folding back into the voice band. AAF is a 2nd order RC low-pass filter.
Converts analog signal to 8bit PCM data according to the companding schemes of
ITU recommendation G.711; A-law or u-law. The band limiting filter is also
integrated. The selection of companding schemes is set by ALAWN register as
follows:
"H": u-Law
"L": A-Law
Expands 8bit PCM data according to A-law or u-law. The selection of
companding schemes is set by ALAWN register as follows:
"H": u-Law
"L": A-Law
Extracts the inband signal from D/A output. It also corrects the sinx/x effect of
D/A output.
Provides the stable analog ground voltage using an on-chip band-gap reference
circuit which is temperature compensated. The output voltage is 2.4V for +5V
operation(AK2306) or 1.5V for +3.3V operation(AK2306LV).
Generates two kinds of tone; 16Hz or 20Hz. Tone selection and Tone ON/OFF is
controlled by the registers.
Gain selects of analog I/O signals. It is posibble to select gain from +6dB to -18dB
(1dB/step). Gain is defined by the internal register.
Interface to the internal register by using SCLK, DATA, and CSN pins.
PLL generates system clock of AK2306. Reference clock is FS (8KHz). More than
0.22uF of an external capacitance should be connected between LPC and VSS.
PCM data rate is available for 64xN(N = 2 to 64)kHz which synchronizes with
BCLK. Two kinds of data format (Long Frame, Short Frame) are available.
Each data format is automatically detected. PCM data stream, which includes
ch0 and ch1 data, is output through DX pin and input through DR pin. Ch1
PCM data stream always follows ch0 PCM data stream.
MS0093-E-04
8
2001/11