AK2306 Datasheet, PDF (6/38 Pages) Asahi Kasei Microsystems – Dual PCM CODEC for ISDN/VoIP TERMINAL ADAPTER

ASAHI KASEI
Pin# Name
1 VFTP1
2 VFTN1
3 GST1
4 GSR1
5 VFR1
6 VR1
22 VFTN0
23 VFTP0
21 GST0
17 VR0
19 VFR0
20 GSR0
10 DX
11 DR
8 FS
9 BCLK
[AK2306/LV]
PIN FUNCTION
I/O
Function
I Positive analog input of the transmit OPamp(AMPT1) for channel 1.
Transmit gain is defined by the ratio of R2/R1.
R1 is the external input resister connected to this pin.
R2 is the external feedback resister connected between this pin and GST1.
I Negative analog input of the transmit OPamp(AMPT1) for channel 1.
O Output of the transmit OPamp(AMPT1) for channel 1.
The external feedback resister is connected between this pin and VFTP1.
O Output of the receive OPamp(AMPR1) for channel 1.
I Negative analog input of the receive OPamp(AMTR1) for channel 1.
Receive gain is defined by the ratio of R4/R3.
R3 is the external input resister connected to this pin.
R4 is the external feedback resister connected between this pin and VR1.
O Analog Output equivalent to the received PCM data for channel 1.
Output gain is adjusted by the GA1R.
I Negative analog input of the transmit OPamp(AMPT0) for channel 0.
Transmit gain is defined by the ratio of R2/R1.
R1 is the external input resister connected to this pin.
R2 is the external feedback resister connected between this pin and GST0.
I Positive analog input of the transmit OPamp(AMPT0) for channel 0.
O Output of the transmit OPamp(AMPT0) for channel 0.
The external feedback resister is connected between this pin and VFTP0.
O Analog Output equivalent to the received PCM data for channel 0.
Output gain is adjusted by the GA0R
I Negative analog input of the receive OPamp(AMTR0) for channel 0.
Receive gain is defined by the ratio of R4/R3.
R3 is the external input resister connected to this pin.
R4 is the external feedback resister connected between this pin and VR0.
O Output of the receive OPamp(AMPR0) for channel 0.
O Serial output of PCM data.
The channel 1 data is output following the channel 0 data. The PCM data rate is
synchronized with BCLK. This output remains in the high impedance state except for the
period of transmitting PCM data.
I Serial input of PCM data.
The channel 1 data is received following the channel 0 data. The PCM data rate is
synchronized with BCLK.
I Frame sync input.
This clock is input for the internal PLL which gerenates the internal system clocks. FS
must be 8kHz clock which is synchronized with BCLK.
I Bit clock of PCM data interface.
This clock defines the input/output timing of DX and DR.
The frequency of BCLK should be 64 x N kHz(128k – 4096kHz).
MS0093-E-04
6
2001/11