AK1541_17 Datasheet, PDF (8/37 Pages) Asahi Kasei Microsystems – 20 to 600Mhz Delta-Sigma Fractional-N Frequency Synthesizer

[AK1541]
2. Serial Interface Timing
<Write-In Timing>
LE
(Input)
CLK
(Input)
DATA
(Input)
Tsu Thd
D19
D18
Tch Tcl
Tlesu ^Tle Tcsu
D0
A3
A2
A1
A0
D19
Fig. 3 Serial Interface Timing
Parameter
Clock L level hold time
Clock H level hold time
Clock setup time
Data setup time
Data hold time
LE Setup Time
LE Pulse Width
Table 5 Serial Interface Timing
Symbol Min.
Typ.
Max. Unit
Tcl
40
ns
Tch
40
ns
Tcsu
20
ns
Tsu
20
ns
Thd
20
ns
Tlesu
20
ns
Tle
40
ns
Remarks
Note 1) LE pin has to be set “Low” after register data setting completed. If LE pin keeps “High” with CLK operation, the
register may not be guaranteed proper setting.
Note 2) While LE pin is setting “Low”, 24 iteration clocks have to be set with CLK pin. If 25 or larger clocks are set, the
last 24 clocks synchronized data are valid.
MS1043-E-05
8
2013/03