AK1541_17 Datasheet, PDF (31/37 Pages) Asahi Kasei Microsystems – 20 to 600Mhz Delta-Sigma Fractional-N Frequency Synthesizer

2. Power-up Sequence
[AK1541]
PVDD,CPVDD
PDN1
On-chip LDO
0V
(1.8V)
Refin
50s
1.8V
Don’t care
Refin must be input before setting [PDN2] to “High”
input
Write to register
PDN2(PLL)
CP
H or L
Registers can be written
After more than 50s from the [PDN1] is set to “High”
Here [PDN1] is set to “High” after or at the same time as power-up.
HiZ
Output(*1)
*1 CP output is not defined before writing the data in
all addresses of the register. After writing them,
CP output can be controlled by register.
Fig. 13 Power Sequence
MS1043-E-05
31
2013/03