AK1541_17 Datasheet, PDF (16/37 Pages) Asahi Kasei Microsystems – 20 to 600Mhz Delta-Sigma Fractional-N Frequency Synthesizer

[AK1541]
 Setup example
DITH = D14 in <Address3> is set to 1:
Available
VCO frequency
180MHz
at the lower limit
[REFIN] pin input
frequency
12.8MHz
{LDCKSEL[1:0]}
0
Formula
180MHz > 12.8/(0+1) x 7 = 89.6MHz
DITH = D14 in <Address3> is set to 0:
Available
VCO frequency
at the lower limit
180MHz
[REFIN] pin input
frequency
12.8MHz
{LDCKSEL[1:0]}
0
Formula
180MHz > 12.8/(0+1) x 4 = 51.2MHz
70MHz
Unavailable
32MHz
2
70MHz < 32/(2+1) x 7 = 74.67MHz
60MHz
Unavailable
32MHz
1
60MHz < 32/(1+1) x 4 = 64MHz
LDCKSEL=0
Reference clock
PFD clock
VCO divide clock
Phase detector output
Lock detect result
ï¼´
Invalid _Valid
Valid
Valid
Invalid
Invalid ^Valid
Fig. 8 Digital Lock Detect Operation
MS1043-E-05
16
2013/03