|
AK4644 Datasheet, PDF (70/96 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP/RCV-AMP | |||
|
◁ |
ASAHI KASEI
[AK4644]
Addr
03H
Register Name
Signal Select 2
Default
D7
D6
D5
D4
D3
D2
D1
D0
LOVL LOPS MGAIN1
0
0
MINL
0
0
0
0
0
0
0
0
0
0
MINL: Switch Control from MIN pin to Stereo Line Output or Receiver Output
0: OFF (Default)
1: ON
When PMLO bit is â1â, MINL bit is enabled. When PMLO bit is â0â, the LOUT/ROUT pins go to AVSS.
MGAIN1: MIC-Amp Gain Control (See Table 23)
LOPS: Stereo Line Output Power-Save Mode
0: Normal Operation (Default)
1: Power-Save Mode
LOVL: Stereo Line Output / Receiver Output Gain Select (See Table 48, Table 49)
0: 0dB/+6dB (Default)
1: +2dB/+8dB
Addr
04H
Register Name
Mode Control 1
Default
D7
D6
D5
D4
D3
D2
PLL3 PLL2 PLL1 PLL0 BCKO
0
0
0
0
0
0
0
DIF1-0: Audio Interface Format (See Table 17)
Default: â10â (Left jutified)
BCKO: BICK Output Frequency Select at Master Mode (See Table 11)
PLL3-0: PLL Reference Clock Select (See Table 5)
Default: â0000â(LRCK pin)
D1
DIF1
1
D0
DIF0
0
Addr
05H
Register Name
Mode Control 2
Default
D7
D6
D5
D4
D3
D2
D1
D0
PS1
PS0
FS3 MSBS BCKP FS2
FS1
FS0
0
0
0
0
0
0
0
0
FS3-0: Sampling Frequency Select (See Table 6 and Table 7) and MCKI Frequency Select (See Table 12.)
FS3-0 bits select sampling frequency at PLL mode and MCKI frequency at EXT mode.
BCKP: BICK Polarity at DSP Mode (See Table 18)
â0â: SDTO is output by the rising edge (âââ) of BICK and SDTI is latched by the falling edge (âââ). (Default)
â1â: SDTO is output by the falling edge (âââ) of BICK and SDTI is latched by the rising edge (âââ).
MSBS: LRCK Polarity at DSP Mode (See Table 18)
â0â: The rising edge (âââ) of LRCK is half clock of BICK before the channel change. (Default)
â1â: The rising edge (âââ) of LRCK is one clock of BICK before the channel change.
PS1-0: MCKO Output Frequency Select (See Table 10)
Default: â00â(256fs)
MS0477-E-01
- 70 -
2006/10
|
▷ |