AK4644 Datasheet, PDF (12/96 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP/RCV-AMP

ASAHI KASEI
[AK4644]
DC CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=2.6 ∼ 3.6V; HVDD=2.6 ∼ 5.25V)
Parameter
Symbol
min
typ
max
Units
High-Level Input Voltage
VIH 70%DVDD
-
-
V
Low-Level Input Voltage
VIL
-
-
30%DVDD V
High-Level Output Voltage
(Iout=−200µA) VOH DVDD−0.2
-
-
V
Low-Level Output Voltage
(Except SDA pin: Iout=200µA) VOL
-
-
0.2
V
(SDA pin: Iout=3mA) VOL
-
-
0.4
V
Input Leakage Current
Iin
-
-
±10
µA
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=2.6 ∼ 3.6V; HVDD=2.6 ∼ 5.25V; C_L=20pF; unless otherwise specified)
Parameter
Symbol
min
typ
max
PLL Master Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
-
27
Pulse Width Low
tCLKL 0.4/fCLK
-
-
Pulse Width High
tCLKH 0.4/fCLK
-
-
MCKO Output Timing
Frequency
fMCK
0.2352
-
12.288
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
40
50
60
256fs at fs=32kHz, 29.4kHz
dMCK
-
33
-
LRCK Output Timing
Frequency
DSP Mode: Pulse Width High
fs
7.35
-
48
tLRCKH
-
tBCK
-
Except DSP Mode: Duty Cycle
Duty
-
50
-
BICK Output Timing
Period
BCKO bit = “0”
tBCK
-
1/(32fs)
-
BCKO bit = “1”
tBCK
-
1/(64fs)
-
Duty Cycle
dBCK
-
50
-
PLL Slave Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
-
27
Pulse Width Low
tCLKL 0.4/fCLK
-
-
Pulse Width High
tCLKH 0.4/fCLK
-
-
MCKO Output Timing
Frequency
fMCK
0.2352
-
12.288
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
40
50
60
256fs at fs=32kHz, 29.4kHz
dMCK
-
33
-
LRCK Input Timing
Frequency
DSP Mode: Pulse Width High
Except DSP Mode: Duty Cycle
fs
tLRCKH
Duty
7.35
tBCK−60
45
-
48
-
1/fs − tBCK
-
55
BICK Input Timing
Period
tBCK
1/(64fs)
-
1/(32fs)
Pulse Width Low
tBCKL 0.4 x tBCK
-
-
Pulse Width High
tBCKH 0.4 x tBCK
-
-
Units
MHz
ns
ns
MHz
%
%
kHz
ns
%
ns
ns
%
MHz
ns
ns
MHz
%
%
kHz
ns
%
ns
ns
ns
MS0477-E-01
- 12 -
2006/10