AK8180D Datasheet, PDF (7/12 Pages) Asahi Kasei Microsystems – 2.5V, 3.3V LVCMOS 1:10 Clock Fanout Buffer

AK8180D
AC Characteristics <2.5V> ⁽¹⁾
All specifications at VDD=VDDA=VDDB=VDDC= 2.5V5%, Ta: -40 to +85℃, unless otherwise noted
Parameter
Symbol
Conditions
MIN
TYP
MAX Unit
Input Frequency ⁽²⁾
fIN
Pin: PCLKp/n
Input Pulse Width
tpwIN
Pin: PCLKp/n
1.4
Peak-to-Peak Input Voltage Vpp Pin: PCLKp/n
500
Common Mode Range ⁽²⁾ Vcmr Pin: PCLKp/n
1.1
Input Rise/Fall time ⁽³⁾
trIN,tfOUT Pin: PCLKp/n 0.8 to 2.0V
Output Frequency ⁽²⁾
DSELx = 0 x1 output
fOUT
DSELx = 1 x1/2 output
250 MHz
ns
1000 mV
VDD-0.7
1.0
ns
250
MHz
125
tPLH
Propagation Delay
PCLKp/n to any Q
1.4
tPHL
Output Disable Time
tPLZ,tPHZ
Output Enable Time
tPZL,tPZH
Within one bank
Output-to-Output Skew
tskPP Any output, same output divider
Any output, Any output divider
2.4
4.4
ns
10
ns
10
ns
150
200 ps
350
Device-to-Device Skew
tskD
Output Pulse Skew ⁽⁴⁾
tskO
3.0
ns
200 ps
Output Duty Cycle
DCOUT DCREF= 50% x1 or 1/2 output
45
50
55
%
Output Rise/Fall Time
tr, tf
0.6 to 1.8V
0.1
1.0
ns
(1) AC characteristics apply for parallel output termination of 50  to VTT.
(2) The AK8180D is functional up to an input and output clock frequency of 350MHz and is characterized up to 250MHz.
(3) Violation of the 1.0 ns maximum input rise and fall tim e limit will affect the device propagation delay, device-to-device skew,
input pulse width, output duty cycle and maximum frequency specifications.
(4) Output pulse skew tskO is the absolute difference of the propagation delay times:| tPLH - tPHL |.
Output duty cycle is frequency dependent (= 0.5  tskO x fout). For example at fout = 125 MHz the output duty
cycle limit is 50%  2.5%.
AC Characteristics <mixed with 3.3V and 2.5V> ⁽¹⁾⁽²⁾
All specifications at VDD, VDDB= 3.3V5%, VDDA, VDDC=2.5V5%, Ta: -40 to +85℃, unless otherwise noted
Parameter
Symbol
Conditions
MIN
TYP MAX Unit
Propagation Delay
tPLH_、tPHL PCLK to any Q
See 3.3V table
ns
Within one bank
150
Output-to-Output Skew tskPP
Any output, same output divider
Any output, Any output divider
250 ps
350
Device-to-Device Skew tskD
Output Pulse Skew ⁽³⁾
tskO
2.5
ns
250 ps
Output Duty Cycle
DCOUT DCREF= 50% x1 or 1/2 output
45
50
55
%
(1) AC characteristics apply for parallel output termination of 50  to VTT.
(2) For all other AC specifications, refer to 2.5V and 3.3V tables according to the supply voltage of the output bank .
(3) Output pulse skew tskO is the absolute difference of the propagation delay times:| tPLH - tPHL |.
Output duty cycle is frequency dependent (= 0.5  tskO x fout). For example at fout = 125 MHz the output duty
cycle limit is 50%  2.5%.
MS1306-E-01
-7 -
Oct-2011