AK8180D Datasheet, PDF (5/12 Pages) Asahi Kasei Microsystems – 2.5V, 3.3V LVCMOS 1:10 Clock Fanout Buffer

Power Supply Current <3.3V>
Parameter
Full operation ⁽¹⁾
Symbol
Conditions
IDD1
CCLK0=250MHz
CLK_SEL=L
Quiescent state ⁽¹⁾⁽²⁾
IDD2
AK8180D
VDD= 3.3V5%, Ta: -40 to +85℃
Min
Typ
Max Unit
95
120 mA
1.6
2.6 mA
(1) The outputs have no loads. (2) All inputs are in default state by the internal pull up/down resisters.
DC Characteristics <3.3V>
All specifications at VDD=VDDA=VDDB=VDDC= 3.3V5%, Ta: -40 to +85℃, unless otherwise noted
Parameter
Symbol
Conditions
MIN
TYP
MAX Unit
High Level Input Voltage
VIH
LVCMOS
2.0
VDD+0.3 V
Low Level Input Voltage
VIL
LVCMOS
-0.3
0.8
V
Peak-to-Peak Input Voltage
Common Mode Range ⁽¹⁾
Input Current ⁽²⁾
High Level Output Voltage
Low level Output Voltage
Vpp
Vcmr
IL1
VOH
VOL
LVPECL
LCPECL
Vin=GND or VDD
IOH= -24mA ⁽³⁾
IOL= +24mA ⁽³⁾
IOL= +12mA
250
mV
1.1
VDD-0.6 V
200 μA
2.4
V
0.55
0.30
V
Output Impedance
14-17

(1) Vcmr(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within t he
Vcmr range and the input swing lies within the Vpp(DC) specification.
(2) Input pull-up / pull down resistors influence input current.
(3) The AK8180D is capable of driving 50  transmission lines of the incident edge. Each output drives one 50  parallel
terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50  series
terminated transmission lines.
(4) IDDQ is the DC current consumption of the device with all outputs open and the input in its default state or
open.
AC Characteristics <3.3V> ⁽¹⁾
All specifications at VDD=VDDA=VDDB=VDDC= 3.3V5%, Ta: -40 to +85℃, unless otherwise noted
Parameter
Symbol
Conditions
MIN
Input Frequency
fIN
Pin: PCLKp/n
0
Input Pulse Width
tpwIN
Pin: PCLKp/n
1.4
Peak-to-Peak Input Voltage Vpp
Pin: PCLKp/n
500
Common Mode Range ⁽²⁾ Vcmr Pin: PCLKp/n
1.3
Input Rise/Fall time ⁽³⁾
trIN,tfOUT Pin: PCLKp/n 0.8 to 2.0V
Output Frequency
fOUT
Pin: Q0-11
0
Propagation Delay
tPLH
PCLK to any Q
1.3
tPHL
Output Disable Time
tPLZ,tPHZ
Output Enable Time
tPZL,tPZH
Within one bank
Output-to-Output Skew
tskPP
Any output, same output divider
Any output, Any output divider
Device-to-Device Skew
tskD
Output Pulse Skew ⁽⁴⁾
tskO
(continued on next page)
TYP
MAX Unit
250 MHz
ns
1000 mV
VDD-0.8
1.0
ns
250 MHz
2.2
3.55 ns
10
ns
10
ns
150
200 ps
350
2.25 ns
200 ps
MS1306-E-01
-5 -
Oct-2011