AKD4687-A Datasheet, PDF (6/52 Pages) Asahi Kasei Microsystems – Evaluation board Rev.2 for AK4687

[AKD4687-A]
„ DIP Switch set up
[SW4] (4687 Mode): Mode settings of AK4687
No.
Name
OFF (“L”)
ON (“H”)
1
I2C
H/W Control
I2C Control
2
AIN1
Analog Input Selector Control (I2C = “L” )
3
AIN0
(Refer to Table 7)
4
MSN
ADC Slave Mode
ADC Master Mode
5
CAD0/CKS
CAD Address pin Control (I2C = “H” )
ADC Master Clock Speed Control (I2C = “L” )
6
TEST1
For AK4687’s TEST MODE (Fixed to “L”)
7
TEST2
For AK4687’s TEST MODE (Fixed to “L” )
X
Table 3. Mode settings of AK4687
Default
L
L
L
L
L
L
L
AK4687
AK4118A (U5)
Register Settings
SW6 Settings
Audio I/F Format
MSN pin DIF1 bit DIF1 DIF0
L
0
L
L
24bit, Left justified
L
1
L
H
24bit,
I S²
P
P
H
0
H
L
24bit, Left justified
H
1
H
H
24bit,
I S²
P
P
Table 4. ADC Audio I/F Format Settings
<Default>
AK4687
Register Settings
DIF21 DIF20
bit
bit
0
0
0
1
1
0
1
1
AK4118A (U6)
SW7 Settings
DIF2
DIF1
DIF0
Audio I/F Format
L
L
L
16bit, Right justified
L
H
H
24bit, Right justified
H
L
L
24bit, Left justified
H
L
H
24bit, I²S
Table 5. DAC Audio I/F Format Settings
<Default>
No. OCKS1 OCKS0 MCKO1
X’tal fs (max)
0
L
L
256fs
256fs
96kHz
1
L
H
256fs
256fs
96kHz
2
H
L
512fs
512fs
48kHz
3
H
H
128fs
128fs 192kHz
Table 6. AK4118A Master Clock Speed Control
AIN1 pin
L
L
H
H
AIN0 pin
L
H
L
H
Input Selector
LIN1 / RIN1
LIN2 / RIN2
LIN3 / RIN3
Reserved
<Default>
Table 7. ADC Input Selector Control (H/W Control Mode)
CKS pin
H
L
Master Clock Speed
256fs
768fs
<Default>
Table 8. ADC Master Clock Speed Control (Master Mode, H/W Control Mode)
<KM104603>
-6-
2011/06