AKD4584_06 Datasheet, PDF (6/46 Pages) Asahi Kasei Microsystems – the 24bit 96kHz CODEC

ASAHI KASEI
[AKD4584]
• Clock setting
(1-1-1) Normal Speed (MCLK=256fs=11.2896MHz@fs=44.1kHz)
JP1
MCKO
JP4
MCLK
JP5
BCFS
JP7
LRFS
M1 M2 x1
x2
x4
x1
(1-1-2) Normal Speed (MCLK=512fs=22.5792MHz@fs=44.1kHz)
JP1
MCKO
JP4
MCLK
JP5
BCFS
JP7
LRFS
M1 M2 x1
x2
x4
x1
(1-1-3) Double Speed (MCLK=256fs=22.5792MHz@fs=88.2kHz)
JP1
MCKO
JP4
MCLK
JP5
BCFS
JP7
LRFS
M1 M2 x1
x2
x4
x1
• SW2 (MODE) setting (See Table 1)
Normal speed and double speed are same setting.
(1) When XTALE is “H”, MCLK can output from MCKO1/2 pins though AK4584 is powered down.
(2) When DMCK is “H”, MCKO1 output is disabled.
H 1 2 3 4 5 6 7 8 9 10
L
<KM065801>
-6-
2006/06