AKD4562 Datasheet, PDF (6/30 Pages) Asahi Kasei Microsystems – EVALUATION BOARD REV.A FOR AK4562

ASAHI KASEI
[AKD4562]
2) Evaluation of D/A using A/D converted data from ideal sine wave generated by ROM data.
Digital signals generated by AKD43XX are used. PORT3 is used for the interface with AKD43XX. Master
clock is sent from AKD4562 to AKD43XX and BCLK, LRCK, SDTI are sent from AKD43XX to
AKD4562. Nothing should be connected to PORT4. In case of using external clock through a BNC
connector (J1), select EXT on JP13 (CLK) and short JP14 (XTE).
JP6
X_BCLK
JP7
LRCK
JP8
BCLK
JP11
SDTI
JP12
DIR
JP13
CLK
JP14
XTE
32fs 64fs ADC DIR ADC DIR ADC DIR VD GND
3) Evaluation of D/A using A/D converted data.
It is possible to make evaluation in the form of analog inputs and analog outputs by interfacing with various
AKM’s A/D evaluation boards with PORT3. Nothing should be connected to PORT4. In case of using
external clock through a BNC connector (J1), select EXT on JP13 (CLK) and short JP14 (XTE).
JP6
X_BCLK
JP7
LRCK
JP8
BCLK
JP11
SDTI
JP12
DIR
JP13
CLK
JP14
XTE
32fs 64fs ADC DIR ADC DIR ADC DIR VD GND
4) Evaluation of D/A using DIR. (Optical link)
PORT4 (DIR) is used. DIR generates MCLK, BCLK, LRCK and SDATA from the received data through
optical connector (TORX176). Used for the evaluation using CD test disk. Nothing should be connected to
PORT3. DIR (CS8412) corresponds to only I²S compatible mode or 16 bit LSB justified.
JP6
X_BCLK
JP7
LRCK
JP8
BCLK
JP11
SDTI
JP12
DIR
JP13
CLK
JP14
XTE
32fs 64fs ADC DIR ADC DIR ADC DIR VD GND
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