AK8181C Datasheet, PDF (6/8 Pages) Asahi Kasei Microsystems – 3.3V LVPECL 1:2 Clock Fanout Buffer

AK8181C
Function Table
The following table shows the inputs/outputs clock state configured through the control pins.
CLK_EN
0
0
1 (Open)
1 (Open)
Table 1: Control Input Function Table
Inputs
CLK_SEL
0 (Open)
1
0 (Open)
1
Selected Source
CLK0
CLK1
CLK0
CLK1
Outputs
Q0, Q1
Q0n, Q1n
Disabled: Low
Disabled: High
Disabled: Low
Disabled: High
Enabled
Enabled
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown in Figure 7. In the active mode, the state of the outputs are a function of the CLK0 and CLK1 inputs as
described in Table 2.
CLK0, CLK1
Disabled
Enabled
CLK_EN
Q0n : Q3n
Q0 : Q3
Figure 7 CLK_EN Timing Diagram
Table 2 Clock Input Function Table
Inputs
CLK0 or CLK1
Q0, Q1
Outputs
Q0n, Q1n
0
Low
High
1
High
Low
Feb-2013
draft-E-01
-6-